Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley March 13-14, 2012 will be an exciting forum for Cadence customers to share their most recent chip design successes and learn from each other. Among close to 100 presentations during the packed two day agenda, one area stands out is mixed-signal design. There are more than 10 presentations with specific focuses on mixed-signal design challenges, and how Cadence tools and flows were used to solve those challenges. Here is a list of related papers in different categories with a list of keywords to highlight the technical contents:

Mixed-signal verification

• Real Number Model (RNM) Model Development and Application in Mixed-Signal SOC Verification by LSI on Tuesday
  • Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification
• AMS Simulation of full duplex USB interface using strength modeled Connect Modules by Texas Instruments on Tuesday
  • Mixed-signal SoC simulation, strength modeling, custom connect modules
• SPEF/DSPF Parasitic Stitching in Post-Layout Analog and Mixed-Signal Simulation by Cadence on Wednesday
  • AMS simulation, parasitic extraction, Spice/Fast-spice
• An Efficient Phase-Locked Loop Noise Simulation Using APS & ViVA by Nvidia on Wednesday
  • PLL simulation, Jitter/noise analysis, Virtuoso® Power System (VPS)
• Verilog-AMS Verification of ADC Soft IP cores by Missing Link Electronics on Wednesday
  • AMS simulation, Verilog-AMS, Spice
• High Performance, Interoperable Real Number Models for Mixed-Signal Verification by Silicon Labs on Wednesday
  • Real number modeling/wReal, mixed-signal SoC simulation, metric driven verification, Virtuoso ADE

Mixed-signal implementation

• IC 61 and EDI 10.1 Inter-Operability Flow, Features and Benefits by Maxim Integrated Products on Tuesday
  • Open Access/OA, unified analog/digital database, analog/digital interoperability, Encounter® Power System (EPS)
• Case Study of Complex High-Speed Mixed-Signal Chip Integration at 40nm by Intersil on Tuesday
  • Analog/digital interoperability, digital-on-top methodology
• Substrate Noise Analysis and Wide Metal Extraction for Power MOS embedded LSIs by Renesas on Wednesday
  • Substrate noise analysis (SNA), wide-metal extraction, QRC

Ecosystem and technology partners

• GLOBALFOUNDRIES 28nm Analog & Mixed Signal Production Ready Flow by Global Foundries on Tuesday
  • AMS reference flow, 28nm, advanced nodes
• AMS Reference Flows for Advanced TSMC CMOS Processes by TSMC on Wednesday
  • AMS reference flow, 28nm, advanced nodes, silicon stress, yield
• From 6 Days to 6 Minutes: Accelerating Mixed-Signal Design Verification by Orora Design Technologies on Wednesday
  • Advanced node, PVT and process variations, mixed-signal SoC simulation, AMS IP integration

 What's Hot/What's Cool 

• A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP by Rambus on Tuesday
  • Power gating, low power mixed-signal designs, CPF, Conformal® Low Power (CLP)
• Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification by Cadence on Wednesday
  • Power aware AMS simulation, CPF, power smart connect modules, CPF generation from Virtuoso Schematic Editor (VSE)

Of course, do not miss the keynote speeches given by executives from ARM, TSMC and Cadence. Go to CDNLive! SV 2012 for more information. See you there next week!

Qi Wang