M/S Technology on Tour Blog – Model Validation and Assertion Based Verification

28 Jun 2011 • 5 minute read

In February 2011, I had the opportunity to meet a group of analog and mixed-signal design and verification engineers in Boston, Austin and Irvine as part of the Cadence Mixed-Signal Tech-on-Tour program. This was a revealing experience for me in many ways. Having been intimately involved with the AMS Designer simulator development for the past 11 years, it was fantastic to see how mixed-signal verification is gaining pace, and how our users are eager to partner with us to solve some of their most challenging verification goals.

Put in another way, it was clear that design evolutions are challenging classic mixed-signal verification techniques and our users and us must together innovate to ensure that mixed-signal verification is no longer an afterthought, but is part of the initial verification plan and that verification task execution must happen in a unified way across the analog and digital boundaries.

During my whirlwind but intensely satisfying journey, several key topics came up for discussion that provided food for further internal brainstorming as I came back. I will briefly touch upon two of these topics here, and describe others in future blogs.

Model validation

As verification at the system level becomes more complex and resource intensive, our users are leaning more and more about building efficient models at different levels of abstraction. A well written model is critical to meeting the right set of verification goals at every stage of verification, ranging from meeting detailed specs at the block level (such as verifying all modes of a programmable gain amplifier, or ensuring typical analog specifications such as distortion or noise figure) all the way to finding the so-called "stupid" errors (connectivity errors, flipped polarity) at the higher level where several blocks with mutual feedback are being integrated.

There is a significant pool of knowledge that exists in the industry today around mixed-signal behavioral modeling. However, there exists another aspect of adopting the modeling approach in verification that must not be overlooked. Deploying behavioral models in block level verification works as a methodology only when there is a scalable and robust way to validate a model against its corresponding schematic.

This is where the Cadence Virtuoso model validation tool (amsDMV) fills a much needed gap, as users from multiple companies came and revealed during informal discussion session. The amsDMV tool provides a simple and automated way to run a set of targeted tests that gives a simple yes/no answer to the model developer if his/her model can reliably replace the schematic for a certain verification goal. This is illustrated by the following graphic:

One interesting request from one of the users I spoke to was the ability to customize the pass/fail criteria so that instead of just comparing the waveforms from the model and schematic driven simulations, the tool is able to perform more complex comparisons using user defined criteria such as behavioral similarity of the two simulations. Another user asked if it was possible to filter the comparison to specific windows in time that satisfied a set of user specified conditions. I believe all these are very valid inputs for the team to consider to make amsDMV truly indispensible in setting up an automated verification methodology based on behavioral modeling.

Assertion Based Verification (ABV) for Mixed-Signal

Our users, specifically the SoC verification leads, are clearly finding the need to incorporate analog and mixed-signal verification goals in to their assertion. This need stems from two core changes that are happening at the mixed signal verification arena.

As part of SOC verification, key blocks that digital verification teams developed their assertion based verification methodology around are being replaced by mixed-signal behavioral blocks for better analog characterization. This immediately implies that the assertion goals for the digital block are not thrown away when its analog counterpart is plugged into the system. Instead, it is expected that the assertion conditions, expressed in standard languages such as Property Specification Language (PSL) or SystemVerilog assertions (SVA), are able to represent analog and mixed-signal expressions so that they can be evaluated along with the rest of the system. An example of this is:

// psl assert always ({V(sig1);a} |=> {V(sig2);b}) @(cross(V(sig3)));

Another type of change that is demanding new envelopes to be explored for assertion is occurring in the pure block-based verification domain. Users here are seeing the need for a more complex language that can accurately capture their verification goals that traditional analog tools such as measurement languages or "assert" devices could not express. Moreover, as verification environments across the digital and analog boundaries get integrated, using a single assertion based verification methodology across digital, mixed-signal and analog worlds mean verification information can be exchanged seamlessly, thereby enabling the dream of unified and plan-based mixed-signal verification to come to fruition.

Toward this end, Cadence PSL and SVA based mixed-signal ABV solutions are useful and a step in the right direction. By using the subsets of PSL and SVA that let users evaluate assertions involving either mixed-signal or real-valued expressions at the digital clock, SoC verification engineers are no longer "shutting down" significant portions of their assertions just because the underlying block has turned into analog.

During my presentation at Austin, one user commented on the need to standardize the analog and mixed-signal assertion language based on SVA. Another user queried about how PSL based assertions could be part of his block based verification. To answer this, I pointed him to the Mixed-Signal Assertion Based Verification Tutorial that is shipped with the Cadence Virtuoso AMS Designer Simulator.

The best part of my journey was in meeting users who wanted to move forward by discarding age old tools that no longer worked in today's design and verification systems. Bolting Verilog and transistor level blocks together without precisely knowing what to verify can be disastrous in a system level verification from a simulation cost/ROI point of view. These users possessed the vision to make changes in the way things are being done, and I felt excited to be part of the discussion where they saw a partner in us to make their dream a reality.

I hope to explore more frontiers in future blogs. I highly encourage users to also refer to the Newsletters and Articles at the Designer's Guide web site where Ken Kundert and Henry Chang have been promoting the "new" style of analog verification and have quite a few success stories to report.

Prabal Bhattacharya