Mixed-Signal Technology Summit in Japan Provides Technology Updates

29 Nov 2012 • 3 minute read

Japan’s semiconductor industry is undergoing a significant change in recent years. We are seeing a shrinking business in SoC development while design and semiconductor companies are trying to focus more on higher profitable and differentiable products like microcontrollers and power management ICs. Most such designs are mixed-signal designs and hence the demand for technologies and innovations in this area is very high.

Since we had our first Mixed-Signal Technology Summit in San Jose in September, we received a lot of positive feedback on the event as it provides a good forum for designers and Cadence experts to share knowledge and inspire innovation on a very specific subject. As a result, Cadence held a similar event in Japan (right) on Nov. 29 in Shin-Yokohama. The event was quite successful with more than 70 attendees from various companies in local areas. In this one day event, Cadence provided the latest technology updates for mixed-signal verification and implementation. In the meantime, we had four partners jointly present with us to demonstrate the importance of the ecosystem to support the fast-changing requirements on mixed-signal designs.

Matlab: MathWorks’ presentation focused on importance of linking system level with IC design. In close collaboration with Cadence they showed how Simulink is used to create a bridge from system design in Matlab to circuit design in Virtuoso® Analog Design Environment and Virtuoso AMS Designer. Particularly for mixed-signal design, it is important to preserve models from the system level to the circuit design level to ensure common specifications are met at SoC level. MathWorks and Cadence worked together to use some of most popular Matlab functional models for mixed-signal designs (like ADC, PLL, Power Switch, RF) in Virtuoso AMS Designer simulators by translating them into C-language models.

ARM: The Cortex-M series of embedded processors become more and more popular in many micro-controller designs targeted for mixed-signal and low power applications. In partnership with ARM, Cadence has developed a demo design to illustrate the ease of mixed-signal SoC verification with software debugging capability using Cadence mixed-signal verification solutions. For more information on this demo project, check out this earlier blog Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums.

TowerJazz: TowerJazz presented the schematic-driven (Analog-on-Top) flow (Go to this link for a video recording of an earlier version of the flow at DAC 2012) for designing power management applications in 180nm and 130nm. The flow leverages Virtuoso as the cockpit and uses the OpenAccess database to integrate digital blocks implemented in Encounter Digital Implementation System. TowerJazz provides a mixed-signal PDK to enable smooth interoperability between Virtuoso and Encounter for improved productivity in floor-planning and chip integration.

Cliosoft: Mixed-signal projects are becoming more and more complex, and consequently data management is becoming mandatory to enable smooth collaboration among analog and digital designers. Cliosoft presented the integration of their data-management tools into Virtuoso, validated in collaboration with Cadence-Japan.

There was a very similar event in Taiwan earlier this week and there will be a smaller one in Korea this Friday. For more information on the Cadence mixed-signal solution, go to the newly constructed website for more technical information and customer success stories.

Qi Wang