Performing Automated Analog Checks by UVM-MS Verification Environment

In this Knowledge Booster blog, we talk about the need to verify analog/mixed-signal blocks using a UVM-MS-based testbench and explore how to verify analog/mixed-signal blocks using the features of MS-MDV and UVM-MS. We also introduce you to the videos and training materials that can help you to ramp up the UVM-MS Methodology.

The UVM-MS approach to checking analog functionality is possibly its biggest departure from current practices in analog design. When using metric-driven verification, there is simply no escape from automatic checking, though manual inspection of waveforms is still frequently used for checking analog correctness. The challenge of automating analog checking is not to replace manual inspection completely but to provide a reasonably good detection of errors for the multitude of batch runs. To do this, deciding which functions and features to check is a major decision during the verification planning phase.

Triggering a Check on Control Changes

Carefully timing a check in a specific test may be good enough for a feature test, but triggering the check automatically is much more powerful. Automatic activation of tests ensures the checked condition is monitored continuously, even when that feature is not targeted. This is especially important when the checker is integrated in a bigger environment where tight control over input timing may not be possible. To determine the activation timing of a check, one has to consider which controls affect the checked condition. These controls are likely to be register settings and external interfaces. Every time any of these controls change, the check should be triggered.

Timing the check requires determining a triggering event to start the measurement on both signals. In the event that there is an expected delay between input and output, the measurements need to be delayed accordingly. The measurement happens over a period of time, at the end of which each monitor provides its output. The final checker code is triggered by the returned measurements. To get a good grab on UVM-MS Accellera standard, take the free Mixed Signal Verification with UVM online course and get yourself certified with the Digital Badge from Cadence Training.

What’s Next?

On the Cadence Learning and Support site (login required)  you can:

• View the Mixed Signal Verification with UVM Training Byte Channel.
• You can Get Your Skills Noticed with a badge from Cadence Training by passing the exam for Mixed Signal Verification with UVM course.
• You can go to the One-Stop Knowledge Resource for Mixed-Signal Verification for more resources on mixed-signal verification and modeling

Related Resources

• Cadence Learning and Support site (login required)
• Related Free Online Courses (support.cadence.com login required):
• Behavioral Modeling with verilog-AMS
• Command-Line-Based Mixed-Signal Simulations with the Xcelium Use Model
• Real modeling with SystemVerilog
• Analog Modeling with Verilog-A

About Knowledge Booster Training Bytes

Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material, on a regular basis.

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Mohammed Jaseem, on behalf of the Cadence Training team