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As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Besides performing Spectre simulations to verify that the design works as expected, you may want to check your design for critical device conditions, or typical design problems, such as high impedance nodes, leakage paths, or power consumption problems. This blog provides an overview of the Spectre assert, the design check, and the Safe Operation Area (SOA) check functionalities and explains when to use which.
Spectre Assert Checks
The Spectre assert checks enable you to check the following in your design for violating a user-defined condition:
Asserts can be defined anywhere in the netlist and can be applied either globally to the entire design, or locally to a subcircuit. Based on the user definition, they create messages in the Spectre logfile in the form of notes, warnings, or errors. Since one design database may contain large numbers of assert checks, you can use the high-level option checklimit to individually enable or disable asserts for any given Spectre DC, Transient, AC, or Noise analysis.
The above figure provides an overview of the assert functionality on a MOSFET example. The assert statement at the bottom of the figure checks all instances of the MOSFET device model nch for VGS>1V and drain current larger than 0.5uA for a duration of 0.1ns. In case of a violation (expression is fulfilled), the assert reports the message “NMOS out of range.” in the Spectre logfile (refer to the red box).
In addition to asserts being used by the design community, some foundries and device model teams use asserts in the device models for detecting devices which operate outside the targeted operation region. Asserts are also supported in Verilog-A modules with the $cds_violation keyword.
A large number of asserts may significantly slow down the simulation. If you are not interested in executing the asserts, you can gain higher performance by using the Spectre -dochecklimit command-line option which disables all assert checks.
Spectre Dynamic Design Checks
Spectre design checks cover the analysis of more complex design problems, such as floating nodes or leakage paths. These problems are caused by combinations of device states that create a special design condition, such as a leakage path caused by all devices in the vdd – gnd path carrying a “leakage” current. Regular asserts can’t detect such scenarios.
There are two types of design checks; dynamic design checks that are performed during transient simulation, and static design checks that are performed during parsing. While static checks detect basic connectivity problems like a MOSFET gate node being floating due to a missing connection, the dynamic checks analyze whether a floating node happens during simulation due to specific stimuli being applied.
You can use the dynamic design checks to analyze the following common design problems (and more):
The figure above illustrates a few of the available checks. The high impedance node check statement at the bottom of the figure analyzes all nodes in the design for a floating condition lasting longer than 2ns. The check is performed in the time window from 1ns to 10ns.
Spectre Static Design Checks
Static checks are based on topology analysis and a voltage propagation, which determine the minimum and maximum voltages for each node. They can be run without performing any Spectre analysis.
Important Spectre static checks detect high impedance nodes, leakage paths, forward biased bulk conditions, transmission gate problems, and long RC delays. They report resistor and capacitor statistics, or provide ERC-like reports for dangling nodes, floating gates, floating bulks, or hot wells.
One of the most common static design checks is the static_voltdomain check which determines whether any low-voltage device has a potential conducting path to a high-voltage power supply. The following example checks the instances of all MOSFET models in the design for any conflicting high and low voltage condition on the same device.
chk1 static_voltdomain model=[*]
Static and dynamic checks need to be defined in the top-level netlist. They can be applied globally to the entire circuit, or locally to selected subcircuit instances. They create XML reports, which can be read with a web browser (refer to the white box in the above figure).
Spectre Safe Operation Area (SOA) Checks
Spectre SOA checks provide a subset functionality of the assert checks described above. They only support terminal voltage checking for a set of predefined device models, including bsim3v3, bsim4, diode, resistor, and bjt.
SOA checks are defined in the device models using a predefined max parameter (for example, vgs_max, vgd_max in the above figure). You can overwrite the device parameter with an instance parameter. The checks create a predefined warning message in the Spectre logfile (refer to the red box in the above figure).
SOA checks are used by selected foundries and device model teams. We recommend that design and CAD engineers use asserts instead of SOA checks because they provide a much more powerful functionality.
Virtuoso ADE Integration
Spectre asserts, design, and SOA checks additionally create SQL output which serves as the base for the Virtuoso ADE integration, or for users who want to apply their own scripts onto the SQL database. You can set up asserts and design checks in the Virtuoso constraint manager; the results are displayed in the violation viewer, and cross probing into schematic editor and waveform viewer is available.
You may also contact your Cadence support AE for guidance.
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