Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise and fall times. They can be separated into dynamic and static checks. Dynamic checks are performed during transient analysis. Static checks are topology checks which do not require any simulation.
In this blog, we'll discuss the high impedance node checks available in Spectre and when to use each check.
Static high impedance node check (static_highz)
The simplest high impedance node check is the static high impedance node check (static_higz). You can use this check to identify connectivity problems in the design, such as a VDD-connected PMOS gate causing a floating node, as shown in the below figure. This check is performed after parsing and does not require any simulation analysis. Although the static_highz check quickly identifies major connectivity problems, it can’t identify any floating node which happens only during a certain time window of a transient simulation.
Dynamic high impedance node check (dyn_highz)
The dynamic high impedance node check (dyn_highz) identifies any floating node during a given time window of the transient simulation. Only the floating nodes that exist for longer than the user-specified duration are reported. The dyn_highz check is stimuli dependent. This means that the floating node is identified only if the stimuli is exercising the floating node scenario. The check reports only the floating nodes. It doesn’t report the leakage paths caused by the floating nodes.
The dyn_highz check has a few limitations. Since a floating node has many possible voltage states, the simulator just picks one representative floating node voltage. On silicon, the floating node voltage may be different.
The check reports all the floating nodes, independent of their severity. Some floating nodes may be expected and may not cause any design problem, while other floating nodes may cause severe leakage current problems. Therefore, it is often a challenge to identify the problematic floating nodes out of the long list of floating nodes reported by the dyn_highz check.
If one floating node is causing another floating node in the later stages of the circuit, the dyn_highz check may not catch the other floating node. Therefore, designers need to first identify the first floating node, fix it, and run the check again to identify any other floating node.
Floating node induced leakage path check (dyn_floatdcpath)
The floating node induced leakage path check (dyn_floatdcpath) performs the checks using a two-step approach. First, it checks for the floating nodes similar to the dyn_highz check and then it sweeps the floating node voltage in multiple steps from 0V to VDD to check for any leakage path related to the floating gate MOSFET.
With the sweeping approach, it overcomes the stimuli dependency of the dyn_highz check. It can safely identify the floating nodes that are causing the leakage path problems between the power supplies or other nodes.
Instead of reporting all floating nodes, the dyn_floatdcpath check reports only the floating nodes that cause severe leakage paths. Alternatively, the check also reports all floating MOSFET’s gate nodes.
The dyn_floatdcpath check has a limitation that it cannot identify the floating nodes that are caused by other floating nodes. The check relies on the user to iterate between running the check and fixing the floating nodes till all the floating nodes are identified and fixed. In addition, the check requires the circuit to be in a stable state at the time the floating node voltage is swept. Therefore, the check doesn't work for high-frequency circuits.
Statistical high impedance node check (dyn_float_tran_stat)
This dyn_float_tran_stat node check combines the node voltage pulling with a statistical method to identify the floating nodes. Its approach is based on randomly pulling the node voltages with a weak driver, up or down. The non-floating nodes are not impacted by the weak voltage pulling while the voltage of the floating nodes is impacted. The check identifies the floating nodes by detecting the device voltage/current changes. The pulling is performed 300 times with statistically random pull up, pull down, or ramp stimuli. This statistical approach allows you to identify any floating node that is caused by another floating node in a 3-node-path (see N1 – N2 – N3 in picture below) with a probability of 99.999%.
This dyn_float_tran_stat check reports the floating nodes and leaking devices. It does not report the path between VDD and GND. Moreover, this check is highly complex and needs careful set up.
In this blog, we discussed the different high impedance node checks and learned when to use each check.
You may also contact your Cadence support AE for guidance.
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