Start Your Engines: Automatic Configuration Creation for a Mixed-Signal Test Bench

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

 

Bonjour!

I hope the year 2021 started well for you.

In this post, I will cover how you can easily create an automatic configuration for a mixed-signal test bench.

Creation of the Virtuoso Hierarchy Editor (HED) configuration in AMS Designer is an important step when you want to simulate a test bench in Virtuosos ADE Explorer or Assembler cockpit.

A configuration enables you to easily select the partitioning for each cell or instance of the test bench. It decides which description objects will be used between transistors or SystemVerilog, Verilog, Verilog-AMS, VHDL, and VHDL-AMS models.

For example, you could start with a Virtuoso mixed-signal design or an existing Virtuoso Schematic-based test bench for analog design instantiating transistors, which has been simulated by Spectre. Follow the steps that I’m giving below to easily simulate it with the AMS Designer simulator.

HED AMS Designer Configuration Creation

Step#1 Open your test bench in Virtuoso Schematic Editor.

Step#2: For automatic config creation, select Launch - Plugins - Mixed Signal Options - Configuration, as shown below.

Step#3: From the new Configuration menu, select Auto Create Configuration.

You will get a confirmation message that the specified configuration is successfully created.

Step#4: Click Launch HED.
This opens the configuration in Table View. Here, you can modify the cell partitioning as needed.

Usually, a designer prefers to use the tree view. To do so, click the Tree View tab.

The tree view displays the hierarchy tree of the Test Bench (TB) and Device Under Test (DUT). Each cell instance has an identifier label. For example, R0 for the resnpoly resistor.

In the tree view, you can define a partitioning custom binding information for a labeled instance. For example, instead of using a transistor sub-circuit schematic, this instance will use a dedicated Verilog-AMS behavioral model view.

After saving the auto_config configuration, you are ready to launch ADE Explorer to run the mixed-signal simulation.

Launching AMSD Test Bench Simulation

Step #5: In HED, click the ADE Explorer button.

Step #6: In ADE Explorer, the simulator is set up for AMS (Spectre). You will need to define the Interface Elements setup, the transient analysis stop time, and the signal or vectors you are interested in plotting.

Step #7: Click () to run the simulation. 

Benefits

• The Virtuoso Schematic AMS Automatic Configuration simplifies the AMS configuration creation.
• In less than 2 minutes, starting from Virtuoso Schematic, you can launch an AMS Designer simulation.
• Any engineer running Spectre simulation in ADE Explorer or Assembler can easily use this feature to convert the test bench to an AMS Designer test bench and run the mixed-signal simulation.

 I wish you a happy experience using the Virtuoso Schematic Editor Automatic Config Creation for AMS Designer.

~ Andre Baguenier

 

Related Resources

• One-Stop Knowledge Resource for Mixed-Signal Verification
• Spectre AMS Designer Product Page

For more information on Cadence circuit design products and services, visit www.cadence.com. 

About Start Your Engines

The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in Spectre AMS Designer, tips for enhanced understanding of existing features, and much more. To receive notifications about new blogs in this series, click Subscribe  and submit your email ID in the Subscriptions box.