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Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity.
In this post, I will explain how you can convert an electrical signal to a logic value using the Verilog-AMS standard language defined by Accellera. I will talk about three behavioral models and their comparison. You can then select the one you prefer for your application.
First, let me draw the symbol for these models.
The model is named E2L_conv and it has:
This model has the following parameters:
vdd supply voltage
Upper threshold for conversion
Lower threshold for analog conversion
Threshold voltage tolerance
Time tolerance of crossing
Analog solver maxstep
The width between vthi and vtlo defines the hysteresis region.
The E2Lconv module can be considered equivalent to an analog comparator. The only difference is that instead of an electrical output, it has a logic value output.
The disciplines.vams file is included in each model to provide the necessary Verilog-AMS discipline definitions (electrical) and the definition of the voltage access function.
This model lets you perform an electrical-to-logic conversion at each analog step of the electrical solver. Inside the analog block, you generate a clock with the aevent variable. The aevent value is initiated at 1 and at each electrical solver step, it is multiplied by -1. The variable aevent toggles iteratively between +1 and -1. In the event solver, inside an always block, cross-event detection is used every time aevent values cross 0. This is done via the always @( cross( aevent, 0, ttol, vtol )) function. This function generates events that force synchronisation between the electrical and digital solvers. In addition, in the analog context, the $bound_step function is used to specify the maximum time allowed between adjacent time points during simulation in the analog solver. By specifying an appropriate time steps value, you can force the simulator to track analog signals as closely as your model requires. When you set a small value for $bound_step, it will slowdown the the transient simulation because of the increased synchronization numbers between the analog and digital solver.
After this, the digital driver of the logic value output is created.
The lout output value with assign statement creates the logic driver in the envent solver.
The testbench is an electrical source with a triangular waveform driving the electrical input. With SimVision MS, you can automatically create the schematic. It also annotates values in the schematic, as shown in the figure. The E2L_conv module described in Verilog-AMS is a mixed-signal model, so the instance is highlighted in blue.
The resultant waveform plots are shown in the given figure.
The idea behind this model is to:
This is done by two always blocks. The first always block is triggered by the V(e) value crossing the vthi theresold on a positive edge. The second always block detects when the V(e) value crosses the vtlo low voltage thereshold on a negative edge.
The resultant waveform plots are as showin in the figure.
This module code reuses the ideas of model 2, but here, both high and low thresholds are dynamically computed based on the supply voltage v(vdd) measured on the testbench. This is done by introducing a new string parameter vddnode, which is an out-of-module reference node name for the testbench supply. In the module, analog context, the Verilog-AMS system function $analog_node_alias creates a mirror or an alias between this internal node vdd to the hierarchical node which is defined via a string reference tb.vdd.
When the voltage V(vdd) changes, the high and low thresholds are updated.
The resultant waveforms plots are as given in the figure.
The testbench simulation results show the E2L_conv operation when v(vdd)=1 volt in the time window 0s to 200ns, and when v(vdd)=2, in the time window 200ns to 400ns. The vthi and vtho threshold values change according to the V(vdd) testbench supply values.
Hope you are now excited to try this feature out yourself! If you need more details, contact your Cadence Support team.
Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Spectre AMS Designer
Spectre AMS Designer Product Page
Start Your Engines: An Innovative and Efficient Approach to Debug Interface Elements with SimVision MS
Start Your Engines: Win Le Mans with the SimVision Mixed-Signal Debug Option
Start Your Engines: Mixed-Signal Modeling Methods for Converting an Electrical Signal to a Real Number
Start Your Engines: Mixed-Signal Modeling Best Practices for Converting a Real Number Signal to Electrical
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- Andre Baguenier