Start Your Engines: Best Practices for Converting an Electrical Signal to a Logic Value with Mixed-Signal Modeling

Cadence Spectre AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune your simulation performance and accelerate down the road to productivity.

 Bonjour!

In this post, I will explain how you can convert an electrical signal to a logic value using the Verilog-AMS standard language defined by Accellera. I will talk about three behavioral models and their comparison. You can then select the one you prefer for your application.

First, let me draw the symbol for these models.

The model is named E2L_conv and it has:

• One electrical input port, named e
• One logic output port named l

This model has the following parameters:

Parameter Name	Description
vdd=1.0	vdd supply voltage
vthi=vdd/1.5	Upper threshold for conversion
vtlo=vthi/2	Lower threshold for analog conversion
vtol=vdd/100	Threshold voltage tolerance
tr=10n	Rise time
ttol=tr/3	Time tolerance of crossing
analogMaxStep=10p	Analog solver maxstep

The width between vthi and vtlo defines the hysteresis region.

The E2Lconv module can be considered equivalent to an analog comparator. The only difference is that instead of an electrical output, it has a logic value output.

The disciplines.vams file is included  in each model to provide the necessary Verilog-AMS discipline definitions (electrical) and the definition of the voltage access function.

Model 1: E2L model conversion operation for each timestep of an analog solver

This model lets you perform an electrical-to-logic conversion at each analog step of the electrical solver. Inside the analog block, you generate a clock with the aevent variable. The aevent value is initiated at 1 and at each electrical solver step, it is multiplied by -1. The variable aevent toggles iteratively between +1 and -1.  In the event solver, inside an always block, cross-event detection is used every time aevent values cross 0. This is done via the always @( cross( aevent, 0, ttol, vtol )) function. This function generates events that force synchronisation between the electrical and digital solvers. In addition, in the analog context, the $bound_step function is used to specify the maximum time allowed between adjacent time points during simulation in the analog solver. By specifying an appropriate time steps value, you can force the simulator to track analog signals as closely as your model requires. When you set a small value for $bound_step, it will slowdown the the transient simulation because of the increased synchronization numbers between the analog and digital solver.

After this, the digital driver of the logic value output is created.

• 1’b1: Specifies that the electrical input is above the high threshold (vthi)
• 1’b0: Specifies that the input signal is lower than or equal to the low threshold (vtlo)

The lout output value with assign statement creates the logic driver in the envent solver.

The testbench is an electrical source with a triangular waveform driving the electrical input. With SimVision MS, you can automatically create the schematic. It also annotates values in the schematic, as shown in the figure. The E2L_conv module described in Verilog-AMS is a mixed-signal model, so the instance is highlighted in blue.

The resultant waveform plots are shown in the given figure.

• The waveform in red displays the electrical input, which is a triangular voltage. It is easy to see the vhti and vtlo threshold.
• The waveform in green displays the logic value output, with conversion operation. The signal transmission to 1’b1 happens when the V(e) value crosses the vthi Similarly, the signal transmission to 1’b0 happens when the V(e) value crosses the vtlo value.

Model 2: E2L Model Conversion Based on Logic Events Controlled by Analog Input Reaching High and Low Thresholds

The idea behind this model is to:

• Trigger the analog and event solver synchronization when the electrical input crosses either the vthi value on positive edge or when the vhlo thresold reaches the negative edge
• Perform an electrical-to-logic conversion

This is done by two always blocks. The first always block is triggered by the V(e) value crossing the vthi theresold on a positive edge. The  second always block detects when the V(e) value crosses the vtlo low voltage thereshold on a negative edge.

The resultant waveform plots are as showin in the figure.

• The waveform in red displays the electrical input, which is a triangular voltage. It is easy to see the vhti and vtlo threshold
• The waveform in green displays the logic value output with conversion operation. The signal transmistion to 1’b1 happens when the V(e) value crosses the vthi Similarly, the signal transmission to 1’b0 happens when the V(e) value crosses the vtlo value.

Model 3: E2L Model Conversion Based on Logic Events Controlled by Analog Input Reaching the High and Low Thresholds while Operating with Dynamic Supplies

This module code reuses the ideas of model 2, but here, both high and low thresholds are dynamically computed based on the supply voltage v(vdd) measured on the testbench. This is done by introducing a new string parameter vddnode, which is an out-of-module reference node name for the testbench supply. In the module, analog context, the Verilog-AMS system function $analog_node_alias creates a mirror or an alias between this internal node vdd to the hierarchical node which is defined via a string reference tb.vdd.

When the voltage V(vdd) changes, the high and low thresholds are updated.

The resultant waveforms plots are as given in the figure.

• The waveform in yellow shows the V(vdd) supply voltage variation at 200ns from 1 volt to 2 volts.
• The waveform in red displays the electrical input, which is a triangular voltage. It is easy to see the vhti and vtlo threshold variation at 2 volts.
• The waveform in green displays the logic value conversion.

The testbench simulation results show the E2L_conv operation when v(vdd)=1 volt in the time window 0s to 200ns, and when v(vdd)=2, in the time window 200ns to 400ns. The vthi and vtho threshold values change according to the V(vdd) testbench supply values.

Common Errors

• For model 1, 2, or 3 : Forgetting to define the cross or above tolerances (the time tolerance or the expression tolerance). It is important to define them because each simulator can have different definitions.
• For model 1: Defining a sampling period using the $bound_step value which is too small or too large versus the electrical signal activity. 

Model Comparison

• Model 1: It has a disadvantage of creating a large number of breakpoints in the electrical solver to provide the E2L conversion accuracy. The breakpoints must be optimized for each application. The AMS simulation can be very slow.
• Model 2: It has good usage, but only if you know the testbench vdd supply voltage in advance. This testbench supply voltage, vdd, should be constant to optimize the vthi and vtlo parameter values to your application requirements before launching the simulation.
• Model 3: Both the vthi and vtlo thresholds follow the testbench supply voltage variations. In addition, it triggers the electrical to logic conversion only when it is mandatory.
• All three models have an infinite analog input impedence.

Conclusion

• Usually, a mixed-signal engineer would prefer model 3. This model has the advantage of adapting itself and smartly supplying values and input signal frequencies on different testbenches. It triggers the synchronization of both analog and event solvers only when this is needed.
• The behavioral electrical-to-logic concepts presented here can be reused for connect module creation with the Cadence Verilog-AMS or SystemVerilog-AMS compilers delivered inside Xcelium. This is very easy. You just need to replace module with connectmodule in the behavioral codes and create a .vams file for the connect rules.
• SimVision MS is very valuable for interactive debugging of such mixed-signal models, with Source Debugger, Design Browser, Waveform window, and Schematic Tracer.

Hope you are now excited to try this feature out yourself! If you need more details, contact your Cadence Support team.

Related Resources

Product Manual	Spectre AMS Designer and Xcelium Simulator Mixed-Signal User Guide
Troubleshooting  Information	Spectre AMS Designer Spectre AMS Designer Product Page
Blogs	Start Your Engines: An Innovative and Efficient Approach to Debug Interface Elements with SimVision MS Start Your Engines: Win Le Mans with the SimVision Mixed-Signal Debug Option Start Your Engines: Mixed-Signal Modeling Methods for Converting an Electrical Signal to a Real Number Start Your Engines: Mixed-Signal Modeling Best Practices for Converting a Real Number Signal to Electrical

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About Start Your Engines

The Start Your Engines series will bring you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.

- Andre Baguenier