Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional Verification Flow

4 Jun 2020 • 2 minute read

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Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

IP reuse…. A term thrown around a lot these days. What does it really mean in terms of Mixed-Signal Functional Verification?

What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent? It’s now made possible with the latest Xcelium mixed-signal technologies from Cadence – the Virtuoso AMS IP export reuse flow.

Preserving the design IP’s integrity during hand-off has always been a major hurdle to overcome as the digital and analog verification worlds are so different. Being able to pass the digital verification chip-lead your signed-off, analog/mixed-signal block as a plug-and-play IP for integration into the digital functional verification environment can have tremendous advantages.

First off, the Virtuoso IP’s cell-view bindings are retained, as they were originally configured and validated in the analog designer’s environment. This introduces opportunities to exercise many flavors of Virtuoso configurations, as they are realized and qualified as static-IP for reuse in the digital functional verification flow.

Second, a higher confidence level for overall functional coverage is achieved for the complete mixed-signal chip if the actual analog content is also exercised by reusing the same digital-centric, Metric-Driven Verification flow. The ability to attain functional coverage for analog is a newer concept and is finally being embraced by analog folks with the aid of long-standing digital techniques.

For instance, let's say the analog/mixed signal block designer has validated the design in Virtuoso with a specific configuration that validates the design function/performance to the functional specification.

Only this specific configuration, with its mix of schematics and behavioral models, meets the specification criteria and at the same time, considers the simulation performance/accuracy trade-off to allow for faster simulations in a digital UVM regression flow.

The analog designer then locks down and packages the Virtuoso configuration into a static, revision-tagged, Virtuoso IP for exportation. This “portable IP package” is then passed over the wall to the digital verification team for full integration into their existing testbench for full chip sign-off.

If you're interested in learning more about what Cadence has to offer in this space, check out the Virtuoso AMS IP Export Reuse Flow Rapid Adoption Kit on Cadence support portal.

Rick Sanborn

Related Resources

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About Start Your Engines

The Start Your Engines! series would bring to you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.