Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC Verification

Cadence^® Spectre^® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev up" your mixed-signal design verification and take the checkered flag in the race to the market. The Start Your Engines! blog series will provide you with tips and insights to help you tune up your simulation performance and accelerate down the road to productivity.

Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the analog IP developers, digital design team, and modeling team in parallel. One of the most challenging aspects is to bring a working mixed-signal/analog IP from the Virtuoso ADE-based environment to the command-line-based system-level simulation. This happens when the mixed-signal/analog IP is ready to replace an HDL-based behavioral model at the system-level simulation. The challenge becomes bigger when the analog IP team, modeling team, and verification team are scattered across geographies.

Semiconductor companies have custom methodology and scripts to bridge the gap between GUI-based Virtuoso mixed-signal/analog IP environment and the command-line simulation flow. Cadence offers a tool, Command Line IP Selector (CLIPS), to streamline importing of mixed-signal/analog IP from the Virtuoso ADE-based environment to command-line-based system-level simulation. CLIPS makes importing Virtuoso IP simple and convenient.

The design verification team can use CLIPS to switch the digital model/representation of an IP to the corresponding analog representation and run verification with ease. CLIPS has several benefits for mixed-signal designers:

• Leverages an existing testbench setup.
• Provides a powerful digital verification mechanism.
• Allows seamless importing of a Virtuoso IP (config view) into an existing digital testbench.
• Eases the verification setup by eliminating the need to import large and complex digital designs in the Virtuoso environment.
• Provides both a GUI-based use model and a command-line-based use model, which are flexible to fit into the design flow methodology.

The figure above shows a SystemVerilog UVM based testbench where a verification engineer wants to replace digital models of LDO and PLL with analog IPs from two different Virtuoso ADE sessions. The two analog IP could be developed by two different teams located at different locations. CLIPS allows you to package these Virtuoso IP for reuse at the SoC verification site, as shown below:

CLIPS supports two use models, command line (Batch Mode) and GUI Mode. For more information and to get some hands-on experience, refer to the Using Command Line IP Selector (CLIPS) on a Low-Power Mixed-Signal SoC Design rapid adoption kit (RAK) on the Cadence support portal. Refer to the Command-Line IP Selector (CLIPS) User Guide for more details.

Lalit Mohan

Related Resources

• One-Stop Knowledge Resource for Mixed-Signal Verification
• AMS Designer Product Page

For more information on Cadence circuit design products and services, visit www.cadence.com. 

About Start Your Engines

The Start Your Engines! series brings you blog posts from several analog/mixed-signal subject matter experts on a variety of topics, such as introduction to the new features in AMS Designer, tips for enhanced working with existing features, and much more. To receive notifications about new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.