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In this series, we will focus on advanced concepts for custom IC design, in particular, variation-aware design (VAD). With emergence of high-speed simulators such as Spectre® APS, designers can now run simulations faster than ever before, so they are able to more completely verify their designs before taping out. However, it requires more than verifying the proper functionality for different stimulus and performance across corner conditions to assure a design is successful. To be successful requires more, it requires properly allocating design margins based on process variation. Designers can not only use the Cadence® Virtuoso® ADE Product Suite to analyze the results and verify the design is specification compliant, reducing the risk of a design respins and getting the product to market faster. It can also increase competitiveness by helping designers reduce the effect of process variation on a design. Solving this problem requires more than fast simulation, it requires adopting new tools and methodologies.
First, let’s consider the impact of over margining to avoid the negative effects of process variation on circuit performance. For example, let’s say we are designing a successive approximation ADC and find that the linearity of the capacitor digital-to-analog converter, CAPDAC, used to generate reference values, limits yield to 90%. Also assume that for the current design, the CAPDAC is 25% of the die area and there are 1000 die/wafer. If we can increase the yield to 99% by doubling the CAPDAC area, should we do it? Working through the numbers, we see that the current design has 900 good die per wafer while the high-yield design has 792 good die wafer, 800 die/wafer * 99% yield. So even though the yield went up, profit will go down. There are two points to consider:
What type of simulation was performed to generate the yield numbers generated? Should the results of these simulations be trusted? These are questions that we also need to consider when making the decision on which design to take to production. In the first part of this series of articles, we will explore variation-aware design. The question to be considered is how to balance the conflicting requirements immunity to process variation against the cost in terms of product competitiveness. In the second half of these articles, we will explore reliability analysis for devices and interconnect. Again, this is an area where designers have traditionally relied on allocating design margin and overdesign to prevent issues. The question to be considered is, as the importance of designing for automotive applications and industrial and infrastructure applications grows, do we have enough design margin? Automotive designs operate in harsher environments and may need to operate reliably for years after a consumer product would have been recycled. The need for these types of solutions has been anticipated and these capabilities already exist in the design environment.
In the next article, we will look into Monte Carlo sampling methods to see how we can minimize the number of simulations required to answer the question of what yield is for the circuit.