Virtuoso Meets Maxwell: TILP! What’s a TILP?

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso supports RF designs, and the RF designers measure the physical and radiation effects by using the Maxwell equations. In addition to providing insight into the useful software and documentation enhancements, this series broadcasts the voice of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso Packaging world. We are posting every alternate Monday.

I have been breathing IC layout design for the last 38 years! Proliferating new Cadence products in the industry has been an enriching experience. Here I come to talk about yet another powerful invention, Virtuoso^® RF Solution and the underlying concepts. These concepts must be understood by designers who know package design but are new to the Virtuoso RF Solution. Or, the IC layout designers who are doing package design in Virtuoso for the first time.

To begin, let us understand what TILP, a significant concept, means. A TILP is a Technology Independent Layout Pcell.

Ok, I have told you what TILP stands for, but we need to delve deeper to see how it fits in the flow. Virtuoso users are very well aware of a Pcell. What is so special about a Technology Independent Layout Pcell?

In IC design, Virtuoso works with an IC PDK, where the layout has an associated technology file that contains the information about known layers and foundry rules. The regular Pcells have the master views designed in SKILL. When these views are instantiated in a layout, a sub-master view is created that derives its physical properties and layers from the technology file associated with the master view.

On the contrary, the concept of a package PDK does not exist in a package design. Consequently, at times, the package layouts are designed before the package layers are known. The package layout view is created with a generic layer within the base cell. The reason being that these layouts need the flexibility to be re-layered on the package layers during instantiation. That's how they are 'independent' and suit for being a TILP.

How Are TILPs Created

TILPs are created differently. There are various options available to source the base cellview as a TILP. For example, importing a layout from an Allegro SiP file, creating a die footprint by exporting the die (Stay tuned for a future blog on Die Export), creating a Surface Mounted Device (SMD) library, or creating a TILP manually by using the GUI options. 

After the base cellview is available for TILP, you will notice some new views in the Virtuoso Library Manager. The views include layout, schematic, and symbol views. Besides, you will spot padstack_base or symdef_base views. The padstack_base view is the generic layout view for components such as vias and pads. The symdef_base view, on the other hand, is usually a ball grid array (BGA) or an embedded component.

When you open the layout view for TILP, you will see the following in the canvas 

And, the thumbnail view appears something like this  

Subsequently, when you open their respective padstack_base or symdef_base views, you will observe generic layers, such as drill, solderMaskTop, or beginGenericLayer. Now, it is evident that the TILPs are 'independent' in true sense. However, to live up to its true purpose, when you instantiate the layout view for TILP in a package layout, the TILP creates the master view. Additionally, the generic layers that are in the padstack_base view are now assigned to the instantiated layout view on the appropriate layer depending on the CDF parameters selected. Isn't it an amazing transformation? Real luxury is customization -Lapo Elkann

This is just the beginning...TILP has a long story to be told.  There are many CDF parameters that can affect the TILP.  For instance, if it is a die, it is flipped. Does it have a shrink factor? Is it embedded in the laminate or mirrored? We’ll explore the answers in the succeeding TILP episodes of the Virtuoso Meets Maxwell series!

At the end of this episode, I will leave you pondering over a block diagram that showcases where TILPs come from and how they fit in the Virtuoso RF Solution. Till next time!

Related Resources

• Virtuoso RF Solution
• What’s New in Virtuoso (ICADVM18.1 Only) 

For more information on Cadence circuit design products and services, visit www.cadence.com.

About Virtuoso Meets Maxwell

Virtuoso Meets Maxwell series includes posts about the next-generation die, package, and board design flow with a focus on reinventing and optimizing the design process to ensure that the designer remains a designer! Keep watching!

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Kerry Judd