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When designing layout at advanced nodes, would you like to:
Do more projects with the same number of people?
Keep the same schedule timelines as for the previous nodes?
Reduce the steep learning curve for junior engineers?
Allow for more deterministic layout quality and schedule?
Do all of the above?
At advanced nodes, the complexity and volume of design rules have been growing exponentially. The first generation of advanced node processes introduced the multi-patterning solution, where selective color assignments to shapes was introduced. Newer technologies at 10nm and below require fully-colored design flows, where every shape must be assigned a color. Design rules are therefore driven by assignment of colors to shapes. Designers can no longer memorize all rules, so doing the same layout takes more time and effort.
With each new node, the density rules are becoming increasingly complex. Density rules involve checking different window sizes for a growing number of layers at different stages of the design process – local, intermediate, block, chip, and so on. Designers can no longer work around these density rules and make it an afterthought. Maintaining local poly and active density around critical devices is important as the density gradients impact matching and performance. If these density gradients are not properly accounted for, designers may see large differences between simulation results and silicon results. At the same time, circuit designers increasingly need a variety of device types and dimensions during the design process.
These challenges at advanced nodes have contributed to the evolution of a row-based structured layout methodology, akin to the digital P&R blocks. The Cadence IP team has been using a row-based methodology since the pre-FinFET days. The original motivation was to minimize the Layout Dependent Effects (LDE) at the smaller planar nodes. Early on, it was not obvious how many microns of dummy devices were required to minimize the density gradients and to achieve a high-level of matching. The trade-off was between using transition regions to negate density gradients and achieving uniform densities across the chip. The latter gave rise to the concept of a row-based methodology, where everything “looks the same” and active devices act as “dummies” to negate the density gradients.
So, how does one come up with a row-based methodology and what does it comprise?
The development of a row-based methodology includes evaluation of the PDK, the Design Rule Manual, the circuit design requirements, and the layout design requirements to arrive at a set of parameters that drive the design process. For example, one of the primary drivers for the height of a row is the active density requirement for the project. Similarly, the width of the track patterns that overlap these rows is driven by the EM requirement for the lower metal layers that drive current into the devices.
The components of a row-based design methodology:
Are a library of correct-by-construction device Pcells that snap together in rows like “a child's building blocks”
The goal is to remove iterations of layout changes and DRC runs for base layers (below M1), where the rule complexity could be high. The Pcells snap to the predefined rows, while accounting for all DRC rules and density targets for the base layers.
Are of approved device sizes, limiting the dimensions available to design the circuit
The goal is to achieve uniformity in the layout. Designers are limited by parameters, such as the number and length of fins, to ensure the minimization of density gradients.
Tip: Initially, the circuit designers may find these limitations challenging. Our experience has, however, shown that this method leads to greater efficiency and fewer design iterations. In general, the very nature of some of the advanced node processes limits the device dimensions for design purposes.
Have fixed row heights for different device types that lets you achieve uniform poly and active density
The goal is to achieve fixed row heights based on the density requirements. It is important to note that the density targets drive the cell dimensions. As to the question of area utilization, it is conceivable that there could be some area hits. Our experience shows that the efficiency benefits outweigh any potential area loss.
Follow periodic colored metal track patterns to achieve DRC- and MPT-correct routing by construction
The goal is to have a structured routing methodology superimposed on the fixed rows, which accounts for lower metal layer electromigration (EM) limits. Color is automatically inherited from these metal track patterns, while ensuring DRC correctness.
Our experience with our internal IP team and other customers has highlighted the following benefits of the row-based methodology:
For more information on Cadence circuit design products and services, visit www.cadence.com.
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