Get email delivery of the Cadence blog featured here
Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso® ADE Assembler and Virtuoso® ADE Explorer is the ability to view the Spectre® Classic Simulator netcap report. This is available from IC6.1.8/ICADVM18.1 ISR13.
We have added a new Results view in Virtuoso ADE Assembler and Virtuoso ADE Explorer, called 'Capacitance' that shows you the net and device capacitance values for your simulation. For each net, the capacitance contribution from the Extracted View, Smart View or the DSPF file is shown in the Info network capacitance table. Terminal capacitance values for the devices are shown in the Info dev capacitance table.
You can now also add your own estimates to nets, and these will be reflected in the table.
The reports can be created over sweeps and corners and even save values at specific times during the simulation.
The tables show a lot of data. But using the powerful in-build filters, you can easily filter the data in the table to locate any critical nets. Hyperlinks from the table highlight the net or device on the schematic.
For more information on Cadence circuit design products and services, visit www.cadence.com.
Virtuosity has been our most viewed and admired blog series for a long time. The series has brought to the fore some less well-known yet very useful software and documentation improvements and has also shed light on some exciting new offerings in Virtuoso. This series broadcasts the voices of different bloggers and experts, who continue to preserve the legacy of Virtuosity and try to give new dimensions to it by covering topics across the length and breadth of Virtuoso, and a lot more. To receive notifications about the new blogs in this series, click Subscribe and submit your email ID in the Subscriptions box.