Virtuosity: What's New in analogLib

12 May 2017 • 4 minute read

It's been a while since analogLib was updated, so we decided to pay some attention to some long standing and popular requests in the recent ISRs!

S-Parameter File Parameterization

In IC6.1.7 ISR6, the ability to use parameterization for the s-param file in the nport instance was added. This provides the flexibility to create the s-param file as a design variable in your simulation test setup. You can very simply now set the s-param file as a design variable. Just select the S-parameter file as Design Var? check box in the Edit Object Properties form as shown below and type the file name in the S-parameter data file text box.

Now you can use the file name “spfile” as a design variable in your simulation setup like this:

This will run a simulation for each file.

You can also use “spfile” in the corner setup to run corner simulations using a process based s-parameter file.

Deepprobe

In IC6.1.7 ISR8, a new component, deepprobe was added to analogLib, allowing you to make a connection from the top-level test bench to an internal net within a subckt block down the hierarchy.

It's easy to add these connections. Just place a deeprobe component on the schematic, open the Property Editor and enter the hierarchical node in the box. For example: b is an internal node in the schematic under I1/I0. This must be specified in the simulator syntax. Note only the Spectre simulator is supported.

The waveform will be plotted on the output node of deepprobe component. You can see the voltage of I1.I0.b is plotted on net C.

Because you can now bring up an internal net to the top level of the schematic using deepprobe, you can also do cool stuff like:

Short two internal nets
Connect a voltage/current source to the internal node

Let's see how to do these...

Short two internal nets

To short two internal nets, place two deepprobe elements on the schematic and connect the output node with 0V DC source. This way nodes “a” and “b” of instance I1.I0 are shorted.

Connect a voltage/current source to the internal node

To connect a voltage or current source to the internal node, place a deepprobe element on the schematic and connect the output node with the desired voltage or current source. You can see here the V0 source is now connected to hierarchical node I1.I0.c.

Additional Features for the vsource & isource Cells

hspiceD Support for vsource and isource Cells

IC6.1.7 ISR10 onwards, vsource and isource cells can be netlisted in hspiceD just by setting the simulator to hspiceD. You can use the same schematic for the hspiceD simulator without making any changes to the CDF or specifying any additional parameters.

PWL File Support

In IC.6.1.7 ISR10, we also added the ability to upload Piecewise Linear (PWL) data from a file. If the isource or vsource cell has the Source type set to pwl, you can click the check box to open a browser to find the pwl file to use for the upload.

Nested Bit Pattern Support

Finally, from IC6.1.7 ISR11, if you use the vsource/isource cells to generate a bit sequence then this has been simplified with the addition of nested bit patterns for Spectre only.

For example:

In the Add Instance form below you can define a pattern such as

111 4(0101) 3(1011) 2(0011)

This means that the evaluated pattern will be 111 then 4 times 0101, 3 times 1011 and 2 times 0011, as shown below

111 0101 0101 0101 0101 1011 1011 1011 0011 0011

Which would look like this in the netlist

Related Resources

For more information on Cadence circuit design products and services, visit www.cadence.com.

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Yagya D Mishra