Virtuoso AI Studio IC26.1 Now Available

The Virtuoso AI Studio IC26.1 production release is now available at Cadence Downloads. The README.txt file in the installation directory provides information about supported platforms and other release compatibility.

IC26.1

Here's a list of the highlights from the Virtuoso AI Studio IC26.1 release:

• Virtuoso AI Studio IC26.1 Overview 
  In IC26.1, Virtuoso Studio transforms to Virtuoso AI Studio, powered by ViraStack AI Super Agent. ViraStack AI Super Agent reinvents analog and custom design by autonomously orchestrating front-to-back agentic workflows, from design intent to layout, leveraging LLMs in the best possible manner. Built on the Virtuoso AI Studio platform and powered by silicon-proven Cadence engines, ViraStack AI Super Agent absorbs the manual effort and iterations in the most challenging analog and custom flows, including design migration, verification, post-layout optimization, and layout generation, while understanding design intent through mental models and making intelligent trade-offs along the way.

Virtuoso AI Studio Design Environment Features

• Managing Windows with Tabbed Window Mode
  Organize and manage design windows more efficiently with the new tabbed window mode in Virtuoso AI Studio. Related windows open as tabs within a unified workspace, making it easier to navigate between design views and reduce desktop clutter. The tabbed interface provides common window management operations such as attach, detach, split, and unsplit directly from the tab context menu, creating a more streamlined and productive design experience.

Virtuoso Analog Design Environment Features

• Securing Data Saved by Virtuoso ADE Product Suite (Virtuoso ADE Artist, Virtuoso ADE Assembler, Virtuoso ADE Explorer, Virtuoso ADE Verifier)
  To better protect the simulation setup data and results databases, the format of maestro, verifier, and setupLib cellviews has been transitioned to the binary format. The format used in the earlier versions made these cellviews more vulnerable to misuse. This change in format helps Cadence strengthen the protection of its intellectual property. 
• Simplifying Device Parameterization and Area Optimization Configuration with the PDK Config Writer (Virtuoso ADE Artist, Virtuoso ADE Assembler)
  Create and manage device parameterization and area optimization configurations more efficiently with the PDK config writer. Using the graphical interface of the PDK config writer, you can easily define devices and parameter ranges, reuse parameterization settings, specify area formulas and operating region specifications, and generate parameter ranges using CDF callbacks. This streamlined workflow reduces the need to manually create or edit JSON-based configuration files.
• Automating Design Parameterization with ClassiC (Virtuoso ADE Artist)
  Accelerate design optimization with ClassiC (Classification of Circuits) by automatically identifying circuit structures and generating parameters, parameter ranges, and operating region specifications. Customize parameterization using configuration files or CDF callbacks and extend structure recognition to user-defined custom structures. ClassiC reduces manual parameterization effort and helps maintain consistent optimization setup across complex hierarchical designs.
• Yield Optimization (Virtuoso ADE Artist)
  Use yield optimization to achieve target yield earlier in the design cycle by accounting for process and mismatch variations during optimization, rather than treating yield analysis as a separate, iterative step. By selectively focusing on statistically sensitive instances and applying common mismatch conditions across DUTs, instances, and subcircuits, yield optimization reduces costly redesign iterations, shortens optimization time, and enables more robust circuits without compromising performance targets.
• Fully Parasitic-Aware (DSPF-Based) Design Optimization (Virtuoso ADE Artist)
  Accelerate layout-aware design optimization with post-layout DSPF parameterization through the full parasitic capability. When device parameterization is enabled and a DSPF is included in the maestro testbench, simulations can account for both electrical and parasitic effects across design points without requiring DSPF re-extraction for every iteration. By reusing an existing DSPF as the baseline, you can evaluate parameter sensitivity earlier, explore optimization opportunities more efficiently, and identify promising design points before performing final extraction and signoff validation.
• Plotting Real and Imaginary Waveform Components for Stability Analysis (Virtuoso ADE Artist, Virtuoso ADE Assembler, Virtuoso ADE Explorer)
  Gain deeper insight into stability analysis results with enhanced plotting capabilities in the direct plot form. You can now visualize the real and imaginary components of input waveforms using the real, imag, and real vs. imag options for stb (stability) analysis. The driving point function also lets you plot Impedance or Admittance results directly, making circuit behavior easier to analyze.
• Filtering and Comparing Operating Point Data Across Corners (Virtuoso ADE, Virtuoso ADE Explorer, Virtuoso ADE Artist)
  Analyze operating point data more efficiently with advanced filtering and multi-corner comparison capabilities in the operating point parameters summary form. The advanced filters check box lets you create custom filtering expressions to quickly locate relevant data. In addition, the 'All' option in the corner list loads data for all corners in a single view, making it easy to compare parameter values for the same instance across multiple corners.
• Sweeping Parameterized Cells and Libraries (Virtuoso ADE Assembler, Virtuoso ADE Explorer, Virtuoso ADE Artist)
  Two new parameters, cellSwap and libSwap, are now available in the variables and parameters assistant. Using these parameters, you can sweep cells within a library or across libraries, sweep multiple libraries, use wildcard-based cell selection, automatically detect pin mismatches, and backannotate optimized results to an existing or new schematic.

Virtuoso Schematic Editor XL

• Enhancing Design Review with Design Intent Integration
  Use the read-only mode to enable design review and validation activities without the risk of inadvertently modifying layout data. In addition, an integrated Design Intent (DI) and Design Review (DRV) flow provides a unified methodology for capturing, implementing, reviewing, and validating design specifications. Together, these enhancements improve the efficiency of the design review process while safeguarding design integrity and preventing unintended modifications. 

Virtuoso Layout Suite Features

• Manage Multiple Copied Design Objects with the Clipboard Assistant (Virtuoso Layout Suite XL)
  Use the Clipboard assistant to store and manage multiple copied design objects, making it easy to reuse content across sessions and windows in Virtuoso Layout Suite. With clipboard assistant, you can quickly capture, lock, save, and reload clipboard buffers, reducing repetitive copy and paste actions and boosting productivity. 
• Dynamic Alignment of Objects (Virtuoso Layout Suite XL)
  Use the dynamic alignment feature to achieve real-time, context-aware alignment of objects. It leverages aspect-based snapping and visual guides for precise object placement. As you create or move layout objects, such as rectangles, paths, and instances, the dynamic alignment feature dynamically highlights reference and target aspects, including edges, midpoints, and pin centers, using paired colors and intelligent filters. This feature is also available in Virtuoso Studio Schematic Editor L and Virtuoso Studio Schematic Editor XL.
• Viewing Object Information with the Object Browser (Virtuoso Layout Suite XL)
  Use the object browser to get a unified view of information for objects selected on the canvas. It helps you view object details, filter and sort results, customize displayed fields, and manage object selections. This feature is also available in Virtuoso Studio Schematic Editor L and Virtuoso Studio Schematic Editor XL, with manual mode capabilities only.
• EMIR Analysis in the Resimulation Flow (Virtuoso Layout Suite EXL)
  The EAD resimulation flow now supports Electromigration and IR Drop (EMIR) analysis. This feature lets you perform EMIR verification directly from the resimulation environment, helping you identify reliability issues without switching workflows.
• View Underlying EM Rule Calculations in EM Calculator (Virtuoso Layout Suite EXL)
  Use the pre-layout EM calculator form to view detailed information about the ICT-EM rules used to calculate EM current limits.
• Support for EM Calculator in the Resimulation Flow (Virtuoso Layout Suite EXL)
  EM calculator in the EAD resimulation flow uses technology information from the EM rule files provided by a foundry, along with associated EM models, to perform calculations.
• Quantus Signoff Licensing in the Resimulation Flow (Virtuoso Layout Suite EXL)
  Use the quantusOverride environment variable and layout net count to specify how Quantus signoff licensing is automatically managed in the EAD resimulation flow.
• LVS-Based Binding Flow (Virtuoso Layout Suite MXL)
  LVS-based binding flow improves binding accuracy during analog layout migration by using LVS query data to bind hierarchical schematic and layout designs. The flow prioritizes active-device binding over dummy-device binding. It supports hierarchical designs by using SVDB data generated by Calibre or Pegasus. 
  
• Designing Structured Arrays with Structured Array Composer (Virtuoso Layout Suite MXL)
  Develop structured array compilers using the structured array composer, a comprehensive set of tools that uses a template-based methodology to create regular structures through the abutment of reusable design elements. The tool includes validation checkers for leaf cells, templates, and generated arrays, along with generators that support schematic adaptation, simulation, and silicon debugging. Use the structured array composer for highly regular designs such as memory architectures, image sensors, datapaths, and field-programmable gate arrays (FPGAs).
  

Virtuoso Heterogeneous Integration Solution Features 

• Supporting Multi-Fabric Package and IC Designs with EMX
  EMX now supports multi-fabric designs that combine package and IC fabrics. It also enables analysis of hybrid bonded designs, allowing directly connected adjacent ICs without the need for solder bumps.
• Streamlining Clarity Simulations with the Multiple Structure Workflow
  The Clarity solver is now supported through the Clarity 3D layout multiple structure workflow, which provides a unified environment for configuring and running Clarity simulations.

For more details on these and all the other new and enhanced features introduced in this release, see:

• What's New in Virtuoso AI Studio IC26.1 (Application Notes)
• Virtuoso AI Studio IC26.1 New

For questions or feedback, write to virtuoso_rm@cadence.com.

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Virtuoso Release Team