Virtuoso Meets Maxwell: Virtuoso RF Compliance Audit Smoothens Die Export

'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF and Virtuoso MultiTech. So, how does Virtuoso meet Maxwell? Now, Virtuoso supports RF designs, and the RF designers measure the physical and radiation effects by using Maxwell's equations. In addition to providing insights into the useful software enhancements, this series broadcasts the voices of different bloggers and experts about their knowledge and experience of various tools in the Virtuoso IC-Packaging world along with the nuances of RF, microwave, and high frequency designs. We are posting on Mondays.

For users familiar with the Virtuoso RF Solution, you know that the Export Die is one of the first steps in the implementation flow. This ensures that the IC can be visible within the package design while running the Edit-In-Concert command. As described by Deepti in her blog, you have seen how we update the Export Die GUI, but quite often the die export fails and the messaging in the CIW can be ambiguous. In this blog, I will discuss a new feature in ICADVM20.1 ISR23 called Virtuoso RF Compliance Audit or simply, Die Audit. While auditing a die, you run various checks for an export die function on an IC layout before actually exporting a die. For any issue that is found during the audit, a marker is created with a description on the ExportDie tab of the Annotation Browser.

To launch the Die Audit GUI, click Module – Virtuoso RF Compliance Audit.

This brings up the die audit or Virtuoso RF Compliance Audit GUI.

By default, all checks are enabled but there can be various undesired violations reported. Therefore, you should have the ability to pick and choose which areas to check. Let me describe each of the checks and highlight the most common ones.

• The Library Check looks if the coverBump or pad cell type have been found in the hierarchy.
• The Terms check will find things, such as if the pin over the bump cell does not match the instTerm. This is a very common occurrence and should be checked in an audit.  
• The IC Symbol checks if the matching symbol for the layout is missing.
• The IO Check looks for overlapping pads or "bumps on bumps".
• The IC Symbol Check looks to see if the schematic pins match the layout pins.
• And the last check, Other Checks, looks for the missing prBoundary or if there are left over markers in the design that need to be cleaned up or deleted.

It is always a good idea to run Check Against Source as some of the checks can be found there. Plus, a habit that I have is to run these checks first at the cell where the bumps or pads are initially instantiated before moving to the top cell.  Sometimes issues can be lurking down the hierarchy and are not reported at the top-level cell, which leads to the die export failure.

Here is an image of the Annotation Browser that shows a number of issues.

It should be noted that both the Export Die and Die Audit features pick the Front Pin Layer as the top metal layer from the techfile, which might not match the pin layer in the bump or pad cell. For example, the pin in the bump cell is on a pin purpose layer and not a drawing layer. In this case, it is best to create a template for both die export and die audit. You can create the template by saving the setup in the Export Die GUI or using the pre-defined syntax. 

For more explanation on die audit and a comprehensive list of all the violations reported, see the Die Audit section in the Virtuoso RF Solution Guide.

Well, I hope this blog has helped explain the features of die audit and that it will help you debug any issues you find while exporting a die. 

Related Resources

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Kerry Judd

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