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Our new AI-powered custom design solution, Virtuoso Studio, leverages our 30 years of industry knowledge and leadership providing innovative features, reimagined infrastructure for unrivaled productivity, and new levels of integration that stretch beyond classic design boundaries. In this blog series, learn how the best analog design tools just got better to help you keep pace with your challenging design issues.
By Girish Vaidyanathan, Sr. Product Marketing Manager, Cadence Design Systems
The complexity of custom designs has significantly increased with advancements in process technology nodes, resulting in longer product lifetimes and shorter expected failure rates.
Chip manufacturers have realized that analog/custom IP is the toughest challenge for layout designers due to the numerous iterations required between circuit and layout designs. Such IPs have the greatest number of iterations between circuit and layout and are the last to finish in the design cycle. Teamwork rises as the mantra to complete such complex designs in time. The oneness culture at Cadence encourages us to look at opportunities in our tools and features to promote collaboration amongst our users. Collaboration and teamwork are crucial in this process, and Cadence's culture fosters collaboration through its tools and features.
There is no better place than Virtuoso Studio to reinforce the culture of collaboration among circuit and layout designers crafting complex analog and custom designs. Schematic Driven Layout (SDL) is the foundational functionality that ensures the layout created by the layout designer matches the circuit that the front-end engineer is designing. An SDL clean layout turns LVS into a mere check in the box.
However, to reduce the iterations and get the correct layout the first time, there are numerous requirements and expectations that the circuit designers need to communicate to the layout designer. Now is the time to sunset the idea of relying on schematic notes or ad-hoc solutions outside the tool. Design Intents feature in Virtuoso Studio enables circuit designers to annotate their expectations, such as matching, shielding, symmetry, high current nets, etc., on the schematic. These design intents are transported to the layout automatically when the layout designer starts the implementation in Virtuoso Layout Suite and can be viewed as glyphs on the canvas for easy edits. The guidelines from the circuit designer can be reviewed and converted to constraints such as Modgen for matched device placement, shielding constraint for the auto-router, etc. The layout designer can mark his comments about the implementation and communicate back to the circuit designer.
Well, conveying the physical implementation intents is insufficient in advanced process nodes or circuits that need high performance or reliability. Electrical information is crucial for layout designers to make sure that electromigration (EM) rules, high voltage DRC rules, self-heating of devices, etc., are properly honored. IR drop on the power network and even on signals should be considered when the layout is being created.
This electrical information can be managed and efficiently passed on between the circuit designer and layout designer through simulation results stored in Virtuoso ADE. The electrical datasets are consumed by the layout and in-design verification, and analysis of parasitics, EM/IR, and DRC ensures that nothing is overlooked in the layout creation process. Simulation-driven (SDR) can utilize the current information from the electrical dataset to suggest appropriate wire sizing as the user creates wires interactively. The ability to consume parasitics from a partial layout into simulation promotes the circuit designer to take the current known good layout and analyze it to see if it still meets the design specification.
Imagine the old world, where lack of such close collaboration means frequent schematic and layout updates in cycles where every edit causes the cycle to repeat. Alternatively, over-designing the circuit with enough margins to absorb the slack caused by lack of communication.
Not anymore with a collaborative approach in Virtuoso Studio! Everybody working on the circuit knows the correct intents and works together for faster design closure by minimizing iterations and ECO.
Design Review is a great example of collaboration among the layout design team. Experts set the standards by defining checklists. The team adheres to it, and it can be peer-reviewed easily inside the layout. This reduces the chances of mistakes in the review process and an audit trail for future root cause analysis.
As the name suggests, Concurrent Layout Editing (CLE) is the cornerstone of teamwork in Virtuoso Layout Suite. When a block gets into the critical path and needs help from more than one layout person to work in the same cell, users don’t need to be tied by the OpenAccess limitation of edit locking on the layout cell view, thereby allowing it to be modified by only one user. With CLE, a layout can now be partitioned into many pieces, simultaneously edited by many users, and finally merged by the block owner. It makes the late cycle ECO, chip finishing, or DRC clean-up tasks parallelized and finished sooner.
In conclusion, the advancements in process technology have led to larger and more complex custom designs, making analog/custom IP the most challenging aspect of design. However, the collaborative approach in Virtuoso Studio, with its Schematic Driven Layout (SDL) functionality, Concurrent Layout Editing (CLE), Design Review, and Design Intents feature, promotes effective communication and teamwork among circuit and layout designers. This results in faster and more efficient design closure, reducing the time required for tasks such as late-cycle ECO and DRC clean-up, and ultimately helps in meeting the increasing demand for product lifetimes while reducing failure rates and time to market.