Accelerate Chip Design with Arm Architecture: Cadence EDA Tools on AWS Graviton

Cadence has qualified its full EDA flow on Arm-based AWS Graviton CPUs, and Annapurna Labs is already using the digital implementation and signoff portion in production.

The semiconductor industry is entering a new phase, defined by AI-scale complexity, faster chip design cycles, and increasing pressure to optimize both performance and power efficiency for data center requirements. To meet this moment, chip design teams can utilize cloud compute infrastructure to efficiently access increased compute capacity capable of running the latest electronic design automation (EDA) flows.

That's why Cadence's EDA tool flow is now qualified to run natively on AWS Graviton. Front-end design and verification, synthesis, place-and-route, and timing signoff all run on Arm^® Neoverse^®-based cloud infrastructure, meaning entire chip design projects can leverage Graviton's compute and cloud elasticity together. Design teams can scale up hundreds of instances during intensive runs and release them immediately afterward, optimizing capacity compared to fixed on-premises clusters.

Together, the three form a closed loop: AWS Graviton instances are designed on Arm, Cadence tools run natively on those instances, and the chips being designed on those instances may themselves be Arm-based.

This has important implications for design teams. Teams can scale infrastructure when workloads spike and dial it back when they do not, using up-to-date processing technology. That flexibility is particularly valuable in advanced-node and AI-driven design environments, where implementation is increasingly iterative, bursty, and computationally intense. The Cadence OnCloud Platform provides cloud infrastructure that supports a full front-to-back design flow, as well as peak capacity to augment on-premises compute environments, all running natively on AWS Graviton.

Powering Agentic AI Chip Design

Annapurna Labs is a world leader in implementing high-performance Arm Neoverse silicon used by AWS. Cadence collaborated with Annapurna when porting the digital implementation and signoff tools to the Arm AArch64 architecture. The initial focus was the Cadence Innovus+ Synthesis and Implementation System for place and route using Graviton4 and Graviton5 instances. But this was quickly expanded to the Cadence Genus Synthesis Solution's RTL design on Graviton5. Annapurna Labs is now designing the future-generation Graviton CPUs using the Cadence flow running natively on Graviton.

Figure 1: Cadence EDA tools in Graviton production, qualified natively on AWS Graviton (Graviton4 / Graviton5), and delivered through the Cadence OnCloud Platform (click to enlarge).

"At Amazon, we don't just design Graviton; we rely on it for our own chip design workflows," said Shahar Even-Zur, VP Technology, Annapurna Labs. "Through our collaboration with Cadence to optimize their EDA tools on Graviton, we're seeing performance improvements that translate directly into faster design cycles and greater engineering productivity, ultimately benefiting our customers."

Arm is also using AWS Graviton instances in the cloud to accelerate the development and implementation of future Arm products.

"As AI drives greater complexity in semiconductor design, engineering teams need development environments that help them move faster, scale seamlessly, and innovate with confidence," said Karima Dridi, VP of Productivity Engineering, Arm. "This collaboration with Cadence and AWS expands support for EDA workflows on Arm-based cloud infrastructure, enabling validated workflows and helping developers realize the performance, efficiency, and scalability benefits of Arm compute across more stages of chip design."

"It has been wonderful to collaborate with Annapurna Labs and Arm to deliver the digital implementation and signoff flow on the Arm AArch64 architecture," said Yufeng Luo, Corp VP Digital Design R&D, Digital and Signoff Group, Cadence. "AWS designing Graviton on Arm Neoverse-based platforms demonstrates the Cadence digital flow is tapeout-ready."

Future-Ready Compute for Semiconductor Design

As AI continues to reshape chip requirements and design methodologies, the infrastructure supporting EDA must evolve as well. The combination of Cadence, Arm, and AWS Graviton points to a future in which semiconductor teams can design more flexibly, scale more efficiently, and move faster with scalable, on-demand cloud infrastructure.

This milestone signals that Arm-based cloud compute is production-ready for semiconductor design. With Cadence OnCloud, design teams can now run the full Cadence EDA flow—from front-end design and verification through implementation and signoff—natively on AWS Graviton, gaining Graviton's price-performance advantage without compromising tool capability. For AI chip startups in particular, this means access to production-grade EDA infrastructure on a pay-as-you-go basis, reducing upfront costs and creating scalable control compared to on-prem infrastructure.

Figure 2: A unified, AI-driven Cadence digital design flow for Arm-based designs, spanning design creation through signoff (click to enlarge).

Looking to Scale Arm Design in the Cloud?

Explore Cadence solutions for Arm-based innovation, or connect with the Cadence Arm ecosystem team to ask questions, discuss your design needs, or request a Rapid Adoption Kit (RAK).

Written by Rod Metcalfe, Sr Group Director, Digital and AI Product Management, Cadence