Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high-performance systems on chip (SoCs) that power a new generation of smart devices. Ambarella's mission is to enable intelligence at the edge, from automotive systems that make our roads safer to security cameras that protect our homes and businesses. They create SoCs for devices that perceive, understand, and react to the world in real time, pushing the boundaries of what's possible in edge infrastructure and physical AI.

The Edge AI Challenge: A Mountain of Data, A Trickle of Power

The world is generating data at an incredible rate, with an estimated 80% originating at the "edge"—in our cars, factories, hospitals, and smart devices. Sending this massive volume of information to the cloud for processing is becoming impractical. It's too slow for applications requiring split-second decisions, too costly for mass-market devices, and introduces significant privacy and security risks.

Ambarella recognized this shift and set out to build a solution that could bring the power of the cloud directly to the device. Their goal was to create an edge AI SoC capable of handling immense generative AI workloads—models with billions of parameters—while simultaneously processing multiple high-definition video streams. This wasn't just about adding an AI accelerator; it required a complete, harmonized system-on-chip. The engineering team faced a formidable set of challenges:

• Massive AI Performance: The SoC needed to run sophisticated vision language models (VLMs) and large language models (LLMs) to provide contextual awareness and natural language interaction, a task typically reserved for power-hungry data centers.
• Extreme Power Efficiency: Every watt counts for edge devices, especially those battery-powered or in tight enclosures. The chip had to deliver its massive performance within an extremely tight power budget of around 15 watts.
• High-Speed Data Throughput: Processing multiple 1080p video streams while running AI models demands incredible data bandwidth. The interconnects within the SoC and to other system components had to be lightning-fast, while architecting the chip to minimize calls to external DRAM, to avoid bottlenecks that would massively limit real-time performance.
• Accelerated Time to Market: The AI landscape moves at a breakneck pace. Ambarella needed to move from architectural concept to silicon in hand quickly to maintain its competitive advantage.

Solution: Cadence IP and Solutions

To conquer these challenges, Ambarella knew it needed more than just a tool vendor; it needed a strategic partner with a deep portfolio of world-class IP and end-to-end design solutions. They turned to Cadence, building on a partnership that spanned five years and multiple product generations. Cadence provided both the critical IP and digital implementation tools needed to bring Ambarella's architectural vision to life and optimize the performance. In parallel, Ambarella's successful collaboration with Samsung Foundry guided the selection of Samsung's proven 5nm process technology—offering a solid foundation for the AI acceleration, system integration, and power efficiency essential for running today's leading multimodal VLMs and LLMs at scale. Together, these collaborations provided a springboard for Ambarella's groundbreaking N1-655 chip.

For many on-premises and physical AI edge devices, interconnect quality is paramount, and Cadence's long-standing stellar performance was a key part of the SoC. Ambarella used Cadence's industry-leading IP for PCIe 5.0 to process massive AI workloads as an ultra-high-speed highway for data to move between the SoC and other critical components.

Beyond the specific VIP, Ambarella employed digital implementation, signoff, and system design solutions from Cadence to design its N1-655 SoC. Cadence's end-to-end flow enabled Ambarella's engineers to integrate the high-speed IP for PCIe 5.0 into the complex 5nm process technology and help manage power consumption across the chip to stay within the strict 15W envelope. Key solutions such as the Innovus Implementation System, Genus Synthesis Solution, Conformal Equivalence Checker, Voltus IC Power Integrity Solution, Tempus Timing Solution, Sigrity X Platform, and Clarity 3D Solver are integral to its workflow.

The Result: Redefining Performance at the Edge

The outcome of this powerful partnership is Ambarella's latest edge AI SoC, the N1-655, a chip that sets a new industry benchmark. It can process LLMs with up to 8 billion parameters while simultaneously decoding 12 streams of 1080p video, all within its remarkable 15W power budget!

This achievement showcases how strategic collaboration accelerates innovation. By pairing Ambarella's visionary architecture with Cadence's proven design technologies and Samsung's cutting-edge process technology, the team successfully delivered a solution that:

• Slashed development time using a streamlined and predictable design flow.
• Achieved significant PPA improvements, unlocking new levels of AI performance at record-low power.
• Ensured mission-critical reliability for demanding applications in factories and security.

Cadence's best-in-class IP solutions are essential for building the chips that power next-generation edge infrastructure and physical AI applications, with Ambarella shipping over 36 million edge AI SoCs, cumulatively. Ambarella's N1-655 is more than just a chip; it's a testament to what's possible when industry leaders work together to solve the future's biggest challenges. This isn't just about performance—it's about enabling real-time multimodal AI models, scaling VLMs and LLMs at the edge, and delivering industry-leading AI performance per watt. As Ambarella, Cadence, and Samsung Foundry look ahead to new projects utilizing 4nm and 2nm nodes, this story of innovation is just beginning.

Watch the full story now: Ambarella's Edge AI Breakthrough: Powered by Samsung Foundry and Cadence.