The semiconductor industry stands at a pivotal moment. As we push toward more advanced nodes and complex architectures, the challenges facing chip designers have never been more demanding. From AI data centers requiring unprecedented performance, to three-dimensional integrated circuits (3D-ICs) pushing the boundaries of what's possible, today's engineers need cutting-edge tools and methodologies to stay competitive and drive high-performance, energy-efficient design advancements.

Cadence Presentations at TSMC OIP

This is why Cadence's participation at the upcoming TSMC Open Innovation Platform® (OIP) Ecosystem Forum represents a must-attend opportunity for semiconductor professionals. Our technical presentations showcase breakthrough solutions—developed in collaboration with TSMC and the OIP ecosystem—that address the most pressing challenges in modern chip design, offering practical insights you can apply immediately to your projects.

• Layout Productivity Improvement Using Virtuoso Studio Advanced Routing Features: This joint presentation by Cadence and Qualcomm highlights how Cadence Virtuoso Studio's advanced routing features simplify the layout process for RF, PM, and PA designs. Explore automation techniques that reduce repetitive tasks, ensure constraint compliance, and accelerate tapeout timelines while boosting productivity.
• High-Performance TSMC A16™ Chip Design Using Cadence Digital Full Flow: Rod Metcalfe explores how Cadence's AI-driven Digital Full Flow supports TSMC A16 designs with advanced features like Super Power Rail implementation, thermal-aware optimization, and AI-driven design closure. Learn strategies to optimize performance and meet the challenges of advanced nodes.
• Analog Design Migration and Optimization Flow: Girish Vaidyanathan presents innovative automated workflows for parasitic-aware analog design migration between advanced nodes, ensuring design integrity through preserved symmetry, matching, and validated performance for successful tapeout.
• Greatly Improve Substrate Layout for 3D-IC Design Flow and Productivity by Using Both Substrate Technology File and EDA Tool: This joint presentation by Ksenia Roze, Cadence, and Takahiro Yamada, IBIDEN, explores IBIDEN's substrate technology file integration with Cadence's Advanced Substrate Router (ASR) tool. Learn how auto-routing features minimize design time and enhance efficiency in 3D-IC workflows.
• Optimizing Hybrid Bond Placement in Heterogeneous TSMC-SoIC® Tapeout Designs: Young Gwon, Cadence, and Seth Merriman, Marvell Technology, provide practical insights into optimizing hybrid bond pads and through-silicon Via placements with Cadence's Integrity 3D-IC platform. Discover strategies to improve alignment, connectivity validation, and streamline design iterations.
• DDR5 12.8Gbps MRDIMM Gen2 for AI and HPC Applications: Kos Gitchev presents this session to discuss Cadence's DDR5 12.8Gbps MRDIMM Gen2, developed with Micron, for groundbreaking memory solutions in AI and HPC applications, delivering unmatched reliability and performance.
• Enabling Large-Scale Integration of 3.5D XPU's With a Combination of TSMC's CoWoS® and SoIC® Technologies: AJ Tufano and Jason Gentry, Broadcom dive into advanced 3.5D package integration using TSMC's CoWoS and SoIC technologies for enhanced design scalability and performance in LLMs and DLRMs.
• Automated Device-Level Placement and Routing (APR) Flow for TSMC A16™ Designs: Aneesh R Shastry explores a new APR flow optimized for TSMC A16 designs, automating key steps like placement and routing, significantly reducing cycle times while maintaining high-value analog design principles.
• Qualcomm Deployment of Cadence Quantus FS for Advanced Node IP Extraction: Federico Politi, Cadence, and Gina Marrello, Qualcomm, discuss how Qualcomm leverages Cadence's Quantus Field Solver for precise, scalable parasitic extraction in advanced node IP designs to meet tight production schedules while ensuring high accuracy.
• Optimized Automated Routing Flow for 3D-IC to Streamline Substrate Layout Generation: Ksenia Roze, Cadence, and Raj Venkatramani, AMD, deliver this join presentation to explore how advanced routing automation reduces design time in complex 3D-IC projects, streamlining substrate layout workflows for improved scalability and efficiency.
• LPDDR6 Memory Solutions for AI Data Centers: Frank Ferro spotlights LPDDR6 advancements in enabling high-speed, scalable memory solutions tailored to AI datacenter demands, leveraging TSMC's advanced nodes.
• Pegasus AI-Driven Automated DRC Fixing in Virtuoso Studio: This presentation by Jac Condella showcases how Pegasus AI accelerates and automates DRC violation fixes within Virtuoso Studio, improving turnaround time and ensuring rule-compliant solutions.
• TSMC N6 to N4 RF Design Migration Using AI Solutions: John Bennett explores advanced AI-driven design migration flows for RF designs, highlighting automation in migration from TSMC N6 to N4 nodes while preserving design integrity and leveraging cutting-edge capabilities in Virtuoso Studio.

Preparing for the Future of Semiconductor Design

The semiconductor industry continues evolving at an unprecedented pace. New applications in artificial intelligence, autonomous vehicles, and edge computing create demands that push traditional design methodologies to their limits. Success requires not just better tools, but also new approaches to design complexity and verification, and collaboration with a comprehensive semiconductor ecosystem like TSMC's OIP.

The Cadence presentations at TSMC OIP Ecosystem Forum will provide glimpses into the future of semiconductor design. By attending, you'll gain insights that help prepare your team for upcoming challenges and opportunities.

Register for the TSMC OIP Ecosystem Forum today!