Cadence EDA Workflows Extend to Microsoft Azure Cobalt 200

As chip designs become more complex, design and verification workloads are becoming increasingly compute-intensive. The rise of AI-driven and agentic workflows adds another dimension, with more automated and iterative tasks increasing the need for flexible compute capacity across the semiconductor design flow.

Cadence is expanding the options available to semiconductor teams by qualifying key Cadence EDA workflows on Microsoft Azure Cobalt 200. The qualification enables supported workflows across design and verification, synthesis, place and route, and signoff to run on Cobalt 200-based Azure virtual machines, giving engineering teams another way to access and scale compute for demanding stages of chip development.

Bringing Cadence EDA Workflows to Cobalt 200

By qualifying the EDA technologies critical for IC and SoC development on Microsoft Azure Cobalt 200, Cadence broadens support for cloud-based EDA environments and extends the infrastructure options available to customers running supported Cadence workloads on Azure.

The qualified technologies span multiple stages of chip development:

EDA stage	Cadence	Qualification status
Design and verification	Xcelium Logic Simulation	Main 2026.03
Formal verification	Jasper Formal Platform	2026.06 FCS
Synthesis and implementation	Innovus Implementation System	2026.11
Timing and signoff	Tempus Timing Solution	26.11-s134_1 and 25.15-s084_1 and forward

The qualification establishes that the above Cadence technologies can run natively on Cobalt 200-based Azure virtual machines in supported configurations. It further extends engineers' choices for Azure across multiple stages of the design flow. Teams can evaluate qualified configurations for workloads ranging from design and verification to implementation and signoff, while taking advantage of Azure's scalability.

The Technology Stack Behind the Collaboration

The Cobalt 200 qualification brings together three layers of the technology stack: the Arm CPU architecture, Cadence EDA software, and Microsoft Azure cloud infrastructure. Each layer plays a distinct role in enabling supported semiconductor design workflows to run on Cobalt 200-based Azure infrastructure.

Partner	Technology /Role	Contribution
Arm	CPU architecture	Provides the Arm CPU architecture underlying Microsoft Azure Cobalt 200.
Cadence	EDA software	Provides EDA technologies across the semiconductor design flow, with supported technologies running natively on Arm and qualified on Cobalt 200
Microsoft Azure	Cloud compute infrastructure with Cobalt 200	Provides Cobalt 200-based Azure infrastructure for running and scaling supported Cadence EDA workflows.

Scaling Compute with Azure

Cloud-based EDA gives engineering organizations greater flexibility in how they provision and manage compute capacity. Instead of provisioning fixed infrastructure for the highest anticipated demand, teams can increase capacity for compute-intensive stages of a project and reduce it when those workloads are complete.

For example, a team running a large verification campaign can provision additional compute instances to execute workloads in parallel. During implementation or signoff, additional capacity can similarly be made available for intensive runs and then released when the work is complete. Design teams can provision additional Cobalt 200 instances during intensive portions of the signoff flow and release that capacity when it is no longer required. This flexibility can help organizations align compute capacity more closely with actual workload demand rather than maintaining dedicated infrastructure for peak utilization.

As agentic design workflows mature, cloud infrastructure can also provide access to AI services and other cloud capabilities alongside the compute resources used to run EDA workloads. This creates an opportunity to match different workloads with the compute and software resources suited to them while retaining the elasticity of the cloud.

From EDA Software to Silicon

The relationship between Cadence and Microsoft extends beyond providing software and infrastructure to customers. Microsoft designs custom silicon for its own Azure infrastructure, and Cadence EDA technologies are part of that development flow. A portion of Cobalt 200 was developed using Cadence tools across the same categories of workloads now qualified to run on Cobalt 200-based Azure virtual machines.

This collaboration creates a closed loop, giving insight into how EDA workloads behave at the instruction, memory, and system level and informs how the silicon is designed; the resulting platform then runs those same workloads for Cadence customers. Across Cobalt 100 and Cobalt 200, this has allowed both companies to apply what they learn from one generation to the next—not as a general-purpose CPU that EDA happens to run on, but as a platform where demanding design and verification workloads were understood as a first-class consideration. For semiconductor teams evaluating cloud infrastructure, that shared context is part of what the Cadence and Microsoft collaboration brings to the design flow.

Collaboration Across Generations of Cloud Infrastructure

The Cobalt 200 qualification extends a collaboration between Cadence and Microsoft across multiple generations of Azure infrastructure. It also brings together the EDA software, cloud infrastructure, and Arm architecture required to support modern semiconductor design workflows.

"Microsoft is a key partner for Cadence, and our collaboration on Cobalt spans multiple generations of Azure silicon. With Cadence EDA workflows now qualified on Cobalt 200, we are extending that collaboration to the latest generation of Azure infrastructure and giving semiconductor teams greater flexibility in how they access and scale compute for demanding design and verification workloads."
– Paul Cunningham, SVP and GM, R&D, Cadence

"Cobalt 200 is designed to provide scalable, efficient compute for demanding HPC workloads such as EDA. Cobalt 200 is architected to sustain per-core performance across the full core count, so teams can run simulation, implementation, and physical analysis workloads without any fall off at full utilization. With Cadence workflows running on Cobalt 200-based Azure virtual machines, design teams can use Azure's elasticity to support changing workload requirements. Along with Azure's high performance storage, adjacency to agentic AI services, and qualification on EDA workflows like Cadence, we believe Cobalt 200 on Azure delivers a compelling solution for semiconductor CAD managers."
– Selim Bilgin, CVP of engineering, Silicon, Microsoft

"Built on Arm Neoverse CSS V3, Microsoft Azure Cobalt 200 delivers the performance needed to help shorten demanding EDA validation cycles. Together with Cadence, we're expanding support for essential semiconductor design tools on Arm-based cloud infrastructure, giving engineering teams greater flexibility to run and scale their workloads."
– Eddie Ramirez, vice president of go-to-market, Cloud AI, Arm

Expanding Cloud Choice for EDA

The qualification of Cadence EDA workflows on Microsoft Azure Cobalt 200 gives semiconductor teams another option for running supported design and verification workloads in the cloud. For teams already using Azure, it provides an opportunity to evaluate Cobalt 200-based infrastructure within supported Cadence EDA flows. For organizations evaluating cloud infrastructure for semiconductor development, it adds another qualified combination of EDA software and cloud compute to consider.

As qualification coverage expands and additional workloads are characterized, Cadence and Microsoft can give semiconductor teams greater flexibility in how they provision and scale compute across the design flow.

Explore Cadence solutions for semiconductor design in the cloud, or connect with a Cadence expert to learn more about qualified Cadence EDA workflows on Microsoft Azure.