Next Steps for the Cadence and SkyWater MPW Service

At Cadence, we are dedicated to nurturing future innovators. Our commitment to education and innovation remains strong, and we strive to eliminate obstacles to accessing the commercial-grade tools and resources essential for academia to flourish. When academia and entrepreneurs lost access to a multi-project wafer aggregator service, threatening the progress of their projects, Cadence partnered with SkyWater to offer a new solution on the SKY130 open-source process.

"In order to prepare the next generation of engineers for an impactful career in the semiconductor industry, we need to enable them to gain practical experience taking ideas from concept to tapeout, by partnering with SkyWater, we've created a solution for academia and early stage start-ups to do just that. We are glad to be providing commercial-grade tools that enable academia to realize their ideas in silicon."

- David Junkin, Academic Network Program Manager, Cadence

The Cadence MPW aggregation service enables engineers to design using any commercial or open-source tool to implement designs on the SKY130 process. By leveraging the open-source SKY130 process and design elements, there is no need for an NDA, eliminating the barriers to access that often blocks students and innovators from gaining the hands-on experience to launch a career or new idea. We successfully supported multiple projects on our first shuttle, enabling multiple students to tapeout for their first time and supporting start-ups to move forward in the crucial stages of funding.

"At SkyWater, we recognize how important it is to expand access to advanced semiconductor manufacturing technology. By collaborating with Cadence to provide multi-project wafer access on our SKY130 open-source process, we are enabling students, researchers, and entrepreneurs the opportunity to gain true tapeout and fabrication experience while bringing their designs to life on a reliable, manufacturable platform. This program strengthens the future talent pipeline while demonstrating how U.S.-based manufacturing can accelerate innovation."

- Percy Gilbert, SVP of Engineering, SkyWater Technology

We're excited to announce the opening of the next shuttle run. Designs can be submitted between now and January 16, 2026. Before getting into details about important dates, requirements, and more, we want to highlight the exciting projects that are going into production from our first shuttle.

"The SiliconJackets submission to the Cadence MPW allowed us to gain insights into how our design might perform under real world constraints. Our members were able to improve their skills and better understand the tapeout process through continual support from Cadence engineers. We are excited to be able to test our 6-stage single core RISCV CPU when our chips come back and use what we learn about its performance to improve our next iteration. Participating in the Cadence MPW allowed us to gain experience using industry standard tools with the flexibility of an open-source PDK and with the generous support network Cadence provides."

- Zachary Ellis, Co-Founder and Former President of SiliconJackets, Georgia Institute of Technology

It's exciting to see students working outside the classroom to innovate. It's also imperative that professors integrate this into their curriculum to help prepare the future workforce with hands-on experience, enabling them to make an immediate impact once they launch their careers.

"It has been remarkable to see the SKY130 PDK emerge as a truly open alternative that not only teaches EDA design principles but also enables fabrication of real silicon. The ability to work with commercial-grade tools and a real foundry—with full DRC rules and without the barrier of restrictive NDAs—fundamentally elevates both the complexity of designs and the educational experience. Every student gains world-class, hands-on exposure and can collaborate more broadly than ever before.

At NC State, we used this opportunity to launch a new industry-style course where students built designs from architecture through tapeout using the SKY130 PDK. One final project integrated a mixed-signal near-field communication (NFC) tag with a Rocket Chip RISC-V processor, requiring cross-domain integration of clocks and power. Students did far more than follow pre-established flows—they learned to construct PCells, debug DRC and LVS rules, and contribute improvements back to an open PDK that benefits the wider community. NCSU's tapeout was partially funded by CLAWS, coming from the workforce development portion of the Chips Act."

- W. Shepherd Pitts, PhD, Professor of ECE, North Carolina State University

Not only does access to advanced technology and manufacturing without the need for an NDA allow for students to learn in the classroom, it also advances the entire EDA ecosystem, by allowing innovators to contribute their learnings and advancements to the open-source community.

"The availability of the open-source SKY130 PDK has been highly impactful for students at UC Berkeley. When previous shuttle options became unavailable, Cadence responded quickly with a replacement shuttle and provided individualized support to help us convert our previous flows to new Cadence-supplied standard cells. The open, nature of SKY130 was critical in enabling us to teach a fully student-run tapeout course—where we could not only guide students through the complete ASIC design process but also share our flows, curriculum, and design ideas publicly. Furthermore, we were able to contribute back to the broader open silicon community through publishing our SKY130 plugins and flows for Berkeley's Chipyard and Hammer open-source agile chip design tools. Doing this is only possible with a design kit that doesn't require signing an NDA and safeguarding proprietary information.

Thanks to this support and funding from the Microelectronics Commons Northwest-AI-Hub Workforce Development Program, two student designs went to silicon on the shuttle: a dual-core RISC-V SoC that includes a student-developed core from a prior undergraduate course, and a RISC-V microcontroller integrating UART, SPI, Quad-SPI, PWM, I²C, and GPIO controllers running at 33MHz. We are deeply grateful to Cadence and SkyWater for their rapid adaptation to change and their support throughout the process."

- Jim Fang, Elam Day-Friedland, Lucy Revina on behalf of UC Berkeley's EECS151Tapeout class, advised by Prof. Borivoje Nikolic

With the launch of the next shuttle, we're excited to see how even more students, educators, researchers, and entrepreneurs can take their access to industry-grade technology and manufacturing resources to turn design ideas into reality.

Important Dates

• Designs can be submitted by January 16, 2026. To start the submission process, reach out to SKY130MPW@cadence.com

• After submission, you can expect feedback within 2 weeks

• Expected Die Delivery: July 2026, subject to change based on SkyWater's fabrication timeline

Program Requirements

• A DRC deck that checks both the manufacturing rules and the recommended rules is available on the SKY130 Process Design Kits (PDK) Downloads Page
• Please note: the PDK will be updated on a regular basis. Check back often for the latest version.
• All submitters will need to:
  • Sign a legal agreement
  • Submit a purchase order, cost of design submissions is $10k-$12k plus tax and shipping and handling
  • Upload OASIS design file to a Cadence-provided FTP site
  • Adhere to design layouts that fit within a 3.588mm x 5.188mm bounding box
  • Add a seal-ring, with integrated die ID (supplied by Cadence) at 0,0 in the top level of the design

Frequently Asked Questions

• How can we submit a design?
  • Reach out to SKY130MPW@cadence.com for more information
• Who can submit a design?
  • This offering is available to all, worldwide. There are no limitations on commercial or non-commercial uses
• Are there limitations on what IP, tool, or collateral can be used for the design?
  • All OASIS design files are accepted
• Will a seal-ring and unique die ID be provided?
  • Yes, it will be instantiated in the top-level of the design. More details in the legal agreement
• What acceptance criteria are required?
  • All designs must pass design rule checks and data integrity checks for manufacturability. The SKY130 Process Design Kit has a DRC deck that checks both the manufacturing rules and the recommended rules. Design owners will be responsible for ensuring the functionality and performance of their designs.
• Can the diced wafers be packaged?
  • Please reach out to Integra or Rochester Electronics, who have packaged SKY130 die previously, or work with a number of other package suppliers
• Why is there a price difference?
  • There will be two process options, one that includes ReRAM and one that does not.

Next Steps

We're excited to see the innovative solutions that will come from enabling academia and entrepreneurs to have access to the same industry tools and processes as major commercial customers. Our goal is to lower barriers to entry and encourage future trailblazers to push the limits of what's possible. What will you design next?

Learn more about the Cadence Academic Network.