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The semiconductor industry has been experiencing strong growth during the past decade. The explosion in new technologies such as 5G connectivity, artificial intelligence, hyperscale computing and autonomous vehicles has been driving demand for new system-on-chip (SoC) devices. Unfortunately, the number of highly specialized designers needed to implement all these new SoCs have not been growing at the same rate, so engineering teams are now under immense pressure to implement more design starts of increasingly complex chips in less time with the same number of engineers. Systems companies are also designing semiconductors to better optimize and differentiate their products. However, they may struggle to staff their teams and could experience project delays. It is now clear that if the semiconductor industry is to grow with these opportunities, engineering teams will have to optimize their productivity to produce more silicon devices in less time.
The world is expected to generate over 180 zettabytes of data annually by 2025, and a whole industry has been created processing and extracting value from just a few percent of this data. On a smaller scale, the same trend is being seen in SoC development. As design size grows, a typical SoC will be implemented using many hierarchical blocks, each block generating large amounts of EDA data during the iterative design process. Some of this information will be reviewed by the engineering teams as the design progresses, but the majority is simply deleted to create disk space for the next project. To allow SoC products to continue growing in size and complexity it is essential this valuable EDA data is systematically and efficiently utilized, providing practical information to the engineering teams enabling faster design closure, and the ability to quickly transfer knowledge between projects. The next era of silicon design excellence will leverage the vast amount of valuable data generated during each SoC design, to deliver better performance, power, and area (PPA) with reduced engineering resources.
The Cadence Joint Enterprise Data and AI (JedAI) Platform delivers an open, enterprise-grade, AI-driven, large scale, cloud-enabled, data analytics environment, optimized for vast quantities of EDA data. EDA data covers a wide range of heterogeneous, structured and unstructured information which is not easy to store and process in general purpose environments. Long gone are the days a design team could import text-based reports into spreadsheets, sort a few columns, and extract some useful information. The Cadence JedAI Platform is a cross-Cadence big data analytics solution, that has been built from the ground up to support EDA type data, such as design data, RTL, netlist, waveforms etc, Workflow data, tools and methodology, and workload data, runtime, memory usage, disk space usage etc. The Cadence JedAI Platform also provides comprehensive application programming interfaces (APIs) and industry-standard scripting tools such as Python, Jupyter Notebook, REST APIs, enabling AI-driven, big data analytic applications (apps) by the customer, allowing engineering teams to visualize data and trends, and automatically generate practical design improvement strategies.
By using the Cadence JedAI Platform, designers can quickly identify trends and optimization to achieve the critical power, performance and area (PPA) objectives while reducing design bottlenecks, resulting in faster design closure with fewer engineering resources.
The Cadence JedAI Platform enables a generational shift from single-run, single-engine algorithms in electronic design automation, to algorithms that leverage big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification flow.
A great example of how Cadence JedAI Platform is being used is the Verisium AI-Driven Verification Platform.
The Verisium platform is built on the Cadence JedAI Platform, natively integrating the Cadence Xcelium, Jasper, and Palladium verification engines. Using the Verisium platform, all verification data, including waveforms, coverage reports, and log files, are brought together in the Cadence JedAI Platform. Machine learning models are built and other proprietary metrics are mined from this data to enable a new class of tools that dramatically improve verification efficiency. The Verisium platform delivers a suite of apps such as AutoTriage, PinDown, WaveMiner, and Debug, leveraging big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs, improving overall verification productivity. By combining the Verisium platform and the Cadence JedAI Platform, a new era of AI-driven verification and debug has been enabled.
Another good example of how the Cadence JedAI Platform is being used across different products, is Cadence Cerebrus Intelligent Chip Explorer, which automates design optimization using reinforcement machine learning and scalable distributed computing, delivering improved PPA more quickly than a manual, iterative approach. To enable the reinforcement learning process, Cadence Cerebrus generates a lot of design metrics data and machine learning models, which the Cadence JedAI Platform can utilize in various ways. For example, based on historical Cadence Cerebrus ML model data, the Cadence JedAI Platform, using AI-driven analytics, can predict and generate a customized ML model for future designs, significantly reducing the run time for Cadence Cerebrus to generate an optimized design. These kinds of productivity benefits can only be achieved by integrating big data analytics into the design optimization process.
The Cadence JedAI Platform is very much a part of the Cadence Intelligent System Design strategy. The Cadence JedAI Platform is how we use data and AI-driven analytics to optimize system and silicon design excellence.
With the Cadence JedAI Platform, Cadence is able to unify its computational software innovations in data and AI, across Verisium AI-driven verification, to Cadence Cerebrus AI-driven implementation and Optimality AI-driven system analysis. In turn, this enables customers to use AI-driven optimization and debug to create multiple designs in parallel with fewer engineers.