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I’ve been thinking lately about the legacy of Gordon Moore, the late Intel co-founder and author of Moore’s Law, which predicted ongoing progress in scaling would lead to a doubling of transistor density every 18 months. It held true for decades, stimulating industry progress and bringing exponential advances in power, performance, and area.
But scaling has gotten much more difficult and costly, and so the question now is, what’s the best way to continue driving exponential progress going forward? After all, hyperscale data centers urgently need greater compute performance and data transfer capabilities, at reduced cost, power, and area. And now as artificial intelligence (AI) is becoming more ubiquitous, other applications are demanding similar compute- and data-intensive processing capabilities–think automotive, mobile, imaging, IoT.
3D Innovations as Options
In response, the industry is moving toward 3D integrated circuits, where the focus is not on planar scaling, but instead on connecting multiple chips in a single package to achieve desired technical metrics. This either can be a true vertical 3D configuration, or it can be a multi-chip architecture known as 2.5D, where two or more chips are placed side-by-side on a silicon interposer.
Both help to create a unique product in the market with differentiated technical specifications at the right cost, but this also creates unique challenges. On one hand, the individual chips can be built and optimized using the most appropriate processes for their intended functions. This is cost-effective and can create additional confidence that these proven die will work the first time in the SoC.
On the other hand, there are still many unresolved issues. For example, although existing tools and methodologies enable a “bottoms up” die-by-die design approach, not all of the components are necessarily optimal for interfacing with each other, or for a particular application. The result? Yes, you guessed it – costly overdesign of individual dies or chiplets, and their interconnects bringing down overall system performance and optimization.
Another headache is that while individual dies or chiplets may have passed signoff checks for static timing analysis, thermal effects, electromagnetic interference, and other concerns, the verification and optimization now need to be extended to the whole system across all the chiplets.
There simply has to be an intelligent way to do top-level aggregation and abstraction for the entire system, taking into account bump planning, interconnect optimization, the placement of chiplets on the package substrate, and so forth. Otherwise, there will be too many design iterations based on incorrect abstraction.
But how to do this most effectively?
Industry’s First Integrated 3D-IC Design Solution
Enter the Cadence Integrity 3D-IC platform, the only tool out there that enables users to achieve significant overall system productivity improvements for 3D-IC design.
It’s not boasting to say that no competing offering even comes close. The Integrity 3D-IC platform is the industry’s first integrated solution for planning, implementation, and signoff of heterogeneous and homogenous 2.5D/3D stacked designs with the integration of multiple chiplets. It consists of multiple modular sub-flows and combines system-level planning and analysis with actual physical implementation and early analysis.
It captures design intent up front, supports abstraction for system planning along with early feedback from system-level effects like thermal and power dissipation, and achieves system convergence through seamless implementation and analysis while taking into account chip and packaging effects.
It supports a bottoms-up approach with the ability to assemble multiple chiplets and supports a top-down approach so that the system can be partitioned according to the overall design constraints. The integrated system passes data seamlessly between the chip and package worlds, yet allows each to be separately implemented and analyzed for die signoff and system-level closure.
TSMC, Samsung Among Early Users
Already, innovators such as TSMC and Samsung are using Cadence’s Integrity 3D-IC platform to create their own proprietary 3D-IC solutions for hyperscale computing, AI, and other emerging high-performance applications.
For TSMC, we recently announced new Integrity 3D-IC design flows to support TSMC’s 3Dblox standard for 3D front-end design partitioning in complex systems. The design flows are optimized for all of TSMC's latest 3DFabric offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS) and System-on-Integrated-Chips (TSMC-SoIC ) technologies.
For Samsung, we recently announced a reference tool flow for the Samsung Advanced Foundry Ecosystem (SAFE) for stacked 3D chips, based on the Integrity 3D-IC platform.
A New Way Forward
Moore’s Law may have slowed down, but 3D-ICs represent a compelling way to get higher bandwidth, lower power consumption, and reduced-area designs without having to resort to traditional process scaling. And it provides a vehicle for design reuse, lower costs, and more confidence the system will work the first time.
And with the Integrity 3D-IC platform, Cadence is uniquely positioned to provide a comprehensive solution for cost-effective design of those 2.5D and 3D-ICs. Moreover, this innovative new design platform enables customers to integrate chiplets at different nodes, thereby allowing design reuse and optimization of the foundry process for each function and the interconnect. I call that a win-win!