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Heterogeneous integration (HI) and SoC (system on chip) are two ways to design and build silicon chips. Heterogeneous integration aims to counter the growing expense and complexity of SoC design by taking a modular approach using advanced packaging technology.
For the past two decades, Cadence has supported the industry in transitioning to an SoC model and we remain dedicated to our customers as they push the boundaries of Moore’s Law, right down to 2nm and perhaps 1nm process nodes in pursuit of more transistors. Now, Heterogeneous integration provides a cost-effective alternative that for many applications may prove to be more suitable than a monolithic SoC.
Let’s look at the differences between these two design processes and the benefits and caveats from each side.
An SoC is an integrated circuit (IC) combining every part of a compute system into a single silicon die. This can include one or more central processing units (CPUs) or processors (low-powered microcontrollers and/or application processors) each with several cores, alongside peripherals like a graphics processing unit (GPU), Wi-Fi, Bluetooth, or 4G/5G cellular modems, memory, and perhaps even storage.
The rise and scaling of SoCs have been one of the most innovative and exciting evolutions in semiconductor technology over the past two decades. In the past, designing a complex compute system meant designing a system using discrete, off-the-shelf components.
Because all the components of an SoC are integrated together onto a single die, SoCs offer an unbeatable optimization of power, performance, and area (PPA). They require a relatively small amount of power to operate, perform compute functions very quickly, and take up far less physical space, meaning the end device can be smaller in form factor, too. SoCs now power billions of devices worldwide, from cars to laptops, smartphones to medical devices.
However, building an advanced monolithic SoC, especially at the latest process nodes (7nm and below), has become increasingly expensive. Below 28nm, the cost per transistor has steadily increased since the industry embraced FinFET in the early 2010s—and the few foundries investing in the latest design nodes have all announced price increases.
Then there are project and non-recurring engineering (NRE) costs to consider. Designing something at 3nm requires design teams of perhaps thousands of engineers working tens of thousands of hours and costing hundreds of millions of dollars, just for the functional verification step.
If you are looking to build an SoC for a mass-market smartphone, you may recoup that investment. But in smaller markets, for example, the defense/industrial spaces where only 1000 or so units are needed, it has become difficult to justify.
Finally, consider the physical limitations. Today’s SoCs are reaching reticle limits: the manufacturing equipment simply can’t handle the growing die sizes without employing expensive stitching technology. Larger chips also have a naturally far higher risk of defects, resulting in lower yield per wafer.
Providing an alternative to advanced monolithic SoCs, heterogeneous integration has become a very attractive option for complex yet cost-sensitive designs.
Heterogeneous integration refers to the use of advanced packaging technologies to combine smaller, discrete chiplets—physically realized and tested (hardened) pieces of IP designed to each perform a particular logical function—into one system in package (SiP).
Think of an SoC as monolithic, heterogeneous integration as modular—integrating different chiplets from different foundries. As each chiplet is manufactured separately and designed to be well below the reticle limit, physically producing the chip is a far easier process. Chiplets may also be designed on any process node; heterogeneous integration could potentially combine 28nm chiplets alongside 2nm chiplets, for example.
While heterogeneous integration is still in its early stages, the integration of different chips and discrete components side by side on a common substrate (ceramic, silicon/glass or organic) is not a new concept. Technologies such as multichip module (MCM) and SiP have been around for decades, each used in a variety of applications.
Heterogeneous integration takes SiP design a significant step forward by combining it with cutting-edge packaging and interconnect technologies such as 2.5D/3D-IC, fan-out wafer level packaging (FOWLP), silicon and glass interposers, and embedded bridges.
It also enables larger, more powerful chips for applications such as HPC and the server market. In these cases, large amounts of memory can be integrated directly into the package itself. This simply isn’t possible on an SoC.
However, heterogeneous integration has its caveats. Design does not get easier with heterogeneous integration, it gets harder. Moving from a single monolithic SoC to a system-level architecture re-introduces considerations that SoCs effectively counteracted, such as thermal, electrical, and mechanical stresses. It’s vital that the correct tools, methodologies, and team collaboration approaches are put in place before attempting to design a heterogeneous integration chip.
Heterogeneous integration also means longer signal paths, more I/Os, and a larger form factor—the enemy of efficient PPA. The form factor of a heterogeneous integration-designed chip will naturally be bigger in the X and Y planes and even Z if 3D stacking is implemented, which it inevitably will be.
Furthermore, the way chiplets are packaged in heterogeneous integration is vital to the success of the chip. This means far greater attention needs to be paid to the packaging technology at the design stage, be it 2.5D, 3D-IC, or some other packaging technology.
The answer to this question depends largely on the application, your budget and the number of products containing your chip that you expect to ship. As more use cases emerge requiring powerful artificial intelligence (AI) and autonomous systems employing high-performance computing (HPC) at the edge, SoC technology is likely to reach the physical limits of its capability. Heterogeneous integration provides a natural next step.
Yet there will always be more applications in which no compromise in PPA is acceptable, in which case an SoC remains the best option.
If you’re unsure which path to take in your next chip design, talk to us. With more than 25 years of advanced packaging experience, we enable our customers to generate higher bandwidth, lower power consumption, and reduce area without traditional process scaling.