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RISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength.
The RISC in RISC-V stands for Reduced Instruction Set Computer, meaning it’s designed to simplify each individual instruction given to the computer.
As RISC-V is an open standard, anyone can implement, customize, and expand the ISA to suit their requirements. RISC-V isn’t the first open ISA: Several older RISC ISAs, including POWER and SPARC, have been released into the public domain as open source. The OpenRISC project has proved popular in academic and hobbyist circles, for example. Yet none have gained the industry-wide traction of RISC-V.
In addition, Cadence’s Tensilica RISC processors are well known for their customizable capabilities. Though not an open standard, Tensilica processors are proven in many DSP applications, such as audio, imaging, communications, and much more. In many instances, a Tensilica DSP can be coupled with a RISC-V processor for control and other functions.
In a word: freedom. Whether you’re a pre-seed start-up, home hobbyist, or industry heavyweight, RISC-V offers a way to design and build a chip for your device, customized to contain everything you need and nothing you don’t.
RISC-V is also an ISA sans frontières. Given the unprecedented geopolitical and supply-chain implications obstructing the free trade of semiconductor technology today, companies from the US and Europe to China and Russia are turning to, and even collaborating in enhancing, RISC-V as a global, open specification. Another key driver for RISC-V’s success is in its flexibility. With Moore’s Law slowing and the cost and complexity of designing a chip skyrocketing, chip designers are turning from process node scaling to embracing specialized computing in answering new compute requirements.
Unlike commercial ISAs, which disallow free modification, RISC-V also allows users to implement custom instructions and extensions enabling highly specialized chips, optimized for unique and specific workloads. Extensions include atomic operations and support for AI and HPC-centric processing such as floating-point math (bfloat), matrix multiply, vector extensions, and quantization.
Much of the initial negativity towards RISC-V was around unbridled customization and the danger this will lead to fragmentation. A key benefit of more tightly controlled commercial ISAs is the ability to port code between different processor IP with minimal adaptation. Remove the controls, and you may end up with thousands of differently customized ‘fragmented’ versions of a processor IP, each only capable of successfully running software specifically written to be compatible with it.
RISC-V International, which coordinates the development of the RISC-V instruction set architecture (ISA), is taking steps to mitigate fragmentation by getting anyone building a custom extension to release it publicly so that it can be ratified and standardized by the RISC-V community.
The industry has been quick to embrace RISC-V, and it shows no sign of slowing. For obvious reasons, academia has embraced RISC-V as a free teaching and learning tool. In enterprise markets, companies of all sizes, down to individuals, are making use of the RISC-V ISA in designing hardware to suit a wide range of applications, including artificial intelligence (AI), virtual and augmented reality (VR and AR, collectively XR), automotive, cloud, high-performance computing (HPC), Internet of things (IoT), storage, edge devices and network infrastructure.
RISC-V is already on a clear path to gain significant market share in the embedded space, in processors used for auxiliary functions outside a device’s main application processor. These are deeply-embedded applications – the end user doesn’t know RISC-V is in the chip, yet it’s there performing key functions like power-up sequencing, state machine control, and voltage trim and monitoring.
Yet every week, we see headlines suggesting RISC-V’s application in high-performance applications, too. In June 2022, a collaboration between university students at Università di Bologna and CINECA, the largest supercomputing center in Italy, resulted in the first RISC-V supercomputer capable of showing balanced power consumption and performance. And in September 2022, NASA announced that its next-generation High-Performance Spaceflight Computing (HPSC) processor will be built on RISC-V.
In theory, the RISC-V ISA is open for anyone to download and use to design their own custom silicon chip. In reality, it’s not that simple.
Consider that, on average, over 75 percent of the time and cost of designing a new chip goes on functional verification – ensuring that a chip will function as it’s supposed to before it’s taped out (physically realized in silicon) – and afterwards, validation.
This process has become ever more expensive as chip designers embrace smaller process nodes. Designing something at 3nm requires design teams of perhaps thousands of engineers working tens of thousands of hours and costing hundreds of millions of dollars just for the functional verification step.
Compared to the costs associated with simulating, designing, and validating a RISC-V chip from scratch, licensing ready-made and pre-validated RISC-V cores from a growing list of commercial IP vendors often makes economic sense. Most vendors offer customization for specialized workloads, too.
Of course, if you’re meeting the economy of scale to enable you to design something truly unique with the RISC-V ISA, you’ll need electronic design automation (EDA) tools capable of working with the RISC-V ISA in simulating, designing, and verifying your design.
Learn more about the tools you need to get started in designing and verifying a RISC-V chip with Cadence.