How Is the Semiconductor Industry Handling Scaling: Is Moore's Law Still Alive?

The chip design industry is going through exciting times. Process nodes with smaller geometries have always enticed chip manufacturers and OEMs, as it helps integrate more functionality over SoC. This reduction in the process nodes has been predicted by Moore's law and achieved through scaling rules as per Dennard's law.

Moore's law held for decades, but with the effective upper bound of clock frequencies, quantum tunneling and interconnects limitations, etc., it is on the deathbed. In addition, as shown in the figure, maximum clock frequency has decreased, and even single-thread performance improvements have slowed considerably.This gives rise to questions such as

• Is Moore's Law still alive, and can we scale further to achieve more functionality over the chip?
• What are the challenges in scaling further?
• With technological advancements and material change, is it possible to move to Angstroms?
• If not scaling, how to achieve the desired performance?

How is the semiconductor industry dealing with such issues to keep up with the requirements?

What are the challenges in bringing up new technology nodes?

With the AI/ML infusion and data-intense applications, the raw computing power doubles in less than six months. It is tough to meet such vexed demands. Further, the rising demand for purpose-built silicon for such performance-hungry applications necessitates more reduced-size transistors over the SoC and new technology nodes. As we scale to the more advanced nodes, the cost and speed of the photolithography process constitute a significant concern.

Designing at advanced nodes has always been challenging, there are many challenges as we down to new technology nodes and scale up, a few of them are listed below

• IR Drop becomes more significant at advanced nodes due to increased resistance at advanced nodes.
• The stress and lithography effect may create severe issues like timing slack and leakage power.
• Early detection of random defects that may arise due to smaller wires.
• More transistors/functionality may lead to bigger die sizes; for instance, HPC chips are large and may affect production economics.
• Increasing compute needs for ML to grow - The industry faces increasing challenges as nodes progress, particularly for machine learning, which increases non-linearly.
• An increase in domain-specific compute leads to requirements for heavily parallelized architectures
• Skyrocketing Chip design costs along with slowing single-threaded performance gains.

How is the Semiconductor Industry Integrating more functionality over SoC?

With innovations, smaller form factors, and increasing customer expectations, the demand for more functionality/transistors over SoC has increased. This increase in transistors has followed Moore's Law for decades, but with data-intensive applications and AI/ML inclusion, this demand has become non-linear. This is interpreted in many ways; some of them say Moore's law is no longer alive, while others deny it and still believe it is alive and evolving.

Chip designers are integrating more transistors over SoC by using heterogeneous integration and moving to newer technology nodes for the desired results and performance.

Usage of Heterogeneous Integration 

The bigger die-size problem can be resolved using the heterogeneous integration of chip components.

Cadence and Heterogeneous Integration

Heterogeneous integration of chip components or 3D-ICs is a practical option for miniaturization and better interconnection. The next generation of sophisticated, intelligent device needs, such as high chip density and terabytes of bandwidth, can be met using the vertical stacking of ICs. Imec and Cadence collaborated to enable advanced software to simplify the 3D design process. 

By offering near-field finite element method (FEM) EM analysis, 3D extraction, modeling, and EM simulation, Cadence's Clarity 3D Solver is made to address EM difficulties while building complex 3D structures on chips, interposers, packages, PCBs, connections, and cables. It has distributed processing capabilities employing a cutting-edge domain decomposition algorithm. Compared to the numerous terabyte machines required for older 3D solvers, it permits the simulation of even enormous structures.

3nm Technology 

Transitioning to 3nm has brought challenges beyond device physics (process development), foundry capacity, and production ramp-up schedule ($$ investment). Apart from this, the interconnect variations also are significant. It poses high integration complexity and requires the lowest power possible for extended battery life. Besides managing the effects of device physics, these newer chips also encounter design bottlenecks throughout the design flow. Cadence supports the 3nm design and helps improve engineering teams' productivity while developing the 3nm rule set.

 Cadence and 3nm Technology

The collaboration has enabled interconnect variation to be measured and improved. Cadence has a complete suite of tools that be used at different stages. This test chip used Cadence Innovus Implementation System and Genus Synthesis Solution. Engineers may produce high-quality designs with the best power, performance, and area (PPA) targets while cutting the time to market with the help of the Cadence Innovus Implementation System. The next-generation, high-capacity Cadence Genus Synthesis Solution increases RTL designer productivity by up to 10X. Cadence and Imec have jointly enabled the 3nm implementation flow for next-generation design innovation.

Moving Beyond 3nm

As the markets for high-performance and low-power semiconductors grow in demand. Samsung hopes to increase the capacity of such cutting-edge process nodes "by more than 3X" by putting 2nm chips into mass production by 2025 and 1.4nm chips into mass production by 2027. In order to produce its 2nm process in 2025 and begin employing a 1.4nm process for production by 2027, it will be improving its gate-all-around (GAA) transistor architecture.

 Reducing the process nodes to 1nm is proposed by Imec in collaboration with major chip manufacturers and EDA companies like Cadence. Imec's Roadmap provides a vision of the upcoming advances in the semiconductor industry and helps define the next generation of tools and software. It has charted the path to semiconductor process technology and chip design below 1nm down to the A2 two-angstrom generation.  Moore's law held up for a long time, but more recently, it has been on life support due to physical limitations of the material, rules of the interconnects, and RC losses. It suddenly started breathing with the recent Roadmap of chip design by Imec, which encompasses sub-'1nm' process nodes. Imec's the three-pronged solution, composed of dimension scaling, new materials, device architectures, and system technology co-optimization (SCTO), helps keep up the momentum and meet the required challenges.

 

As per Imec, Ultra-scaled transistors with material such as molybdenum disulfide (MoS2) help develop next-generation electronic devices. It enables density scaling and, hopefully, some performance improvement.

Summary

Scaling brings significant new challenges due to changes in metal, temperature, power, and yield becoming a bottleneck in the design flow process. Packaging, new material innovations, manufacturing technology, and design are the pillars of achieving the desired performance and integration over SoC. Imec envisions a broader view beyond 2030, where new materials will replace silicon and the emergence of 2D atomic channels. Imec believes that magnetics-based gates could emerge as an alternative as the industry moves toward quantum computing inexorably. Cadence is a leader in advanced node design. Over the past few years, we have re-invented the engines to develop a revolutionary digital full-flow toolset to address these design challenges at the design creation, implementation, and signoff stages.