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As a member of the EDA community, I find it interesting and somewhat frustrating to see how much we copy each other at times. Ever notice how one company might make a position on something, and once their message resonates, then a lot of other companies come out of the woodwork with me-too messaging and positioning?
I saw this happen on mixed-signal design, and now see it happening on signoff analysis.
Here at Cadence, we have developed a very comprehensive suite of signoff analysis solutions, and have been advocating that these solutions help design teams more when solutions are integrated into the design environment. Instead of transferring gigabytes of design data to separate tools, it makes obvious sense to enable the analysis directly from the design environments themsleves. This helps design engineers more efficiently execute the multiple types of analysis and enables an easy path to fixing any identified problems -- but it does require signoff levels of accuracy.
Today, signoff solutions at Cadence include functionality used to validate timing, signal integrity, distributed power dissipation, power rail IR drop and electromigration, parasitic extraction, DRC, LVS, noise and on-chip thermal analysis. All of this functionality is now accessible directly from the Encounter Digital Implementation System digital design platform, and most of this functionality is also accessible directly from our Virtuoso custom design platform too. The end result is that we have enabled our customers with high increases in ease-of-use and efficiency in completing their designs.
I find it a little amusing that some of my competition use phrases such as "in-design signoff" when they are often referring to limited functionality such as DRC and LVS. While it is great that they have copied the Cadence positioning, the reality is that true integrated signoff covers a lot more functionality.
If you want to learn more on how Cadence has enabled comprehensive in-design signoff, watch out for some techtorials that will be announced in the coming weeks, where will will educate you in detail on our solutions and the value of the integration.
Dear Sir, I am happy to learn on cadence EDA tool. This signoff solutions covers all design methdologies so I want to watch out some technical tutorials on this design flow.