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I mentioned in my first blog one of my roles in customer support is to identify and author knowledge content for Cadence Online Support (http://support.cadence.com). In this blog post I want to highlight some of the popular Encounter Design Implementation (EDI) System content published in recent months.
If you're not receiving email notifications on the latest Cadence Online Support content, log in to http://support.cadence.com and My Support -> My Account then click on the Notification Preferences tab. Here you can specify the type of content you want to be notified of and the frequency.
There were several new videos and application notes posted recently. AOCV is definitely a hot topic lately:
Additionally, below are the solutions published in recent months which customers viewed the most. I hope you enjoy these highlights!
Adding decap cells near clock buffers or flip-flops
Provides a script to place decoupling capacitors (decap cells) near clock tree buffers or even flip-flops. These cells can have a high current draw so inserting decap cells minimizes the current draw effects.
Script to convert config file to global variable file for init_design in EDI 11
The Design Import flow in EDI 11 uses global variables in place of the config file. This solution provides a script for converting the EDI 10.1 config file to a global variables file. It also updates your environment to MMMC if needed.
Step-by-step through a top-down hierarchical design flow
An easy to follow description of the steps to import a large design with blackboxes and go through a top-down hierarchical partitioning in EDI System.
Using generateVias to create optimal vias for NanoRoute
Shows how to simplify your via definitions in your technology LEF using the generateVias command.
What is the encounter.logv file written out by EDI 11?
Answers the common question, "What is this encounter.logv file?".
How to Search-and-Repair after Post-Route Timing Closure
Simple flow to delete and re-route nets Verify Geometry reports violations on.
assembleDesign does not support one step assembly with nested partitions until EDI 11
Clarifies support for one step design assembly with nested partitions using assembleDesign
Does optDesign fix max transition violations on nets which have set_case_analysis constraint?
Explains optDesign will fix max transition violations even if the net is constant.
Can I update Tech LEF on the fly in Encounter? No.
Explains what LEF data can be loaded incrementally.
How do you balance skew between clocks using CTS?
Shows how to use ClkGroup in the CTS constraints file to balance skew between clocks.