Cadence® system design and verification solutions, integrated under our System Development Suite, provide the simulation, acceleration, emulation, and management capabilities.
System Development Suite Related Products A-Z
Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.
Full-Flow Digital Solution Related Products A-Z
Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.
Overview Related Products A-Z
Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.
Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.
An open IP platform for you to customize your app-driven SoC design.
Comprehensive solutions and methodologies.
Helping you meet your broader business goals.
A global customer support infrastructure with around-the-clock help.
24/7 Support - Cadence Online Support
Locate the latest software updates, service request, technical documentation, solutions and more in your personalized environment.
Cadence offers various software services for download. This page describes our offerings, including the Allegro FREE Physical Viewer.
Get the most out of your investment in Cadence technologies through a wide range of training offerings.
This course combines our Allegro PCB Editor Basic Techniques, followed by Allegro PCB Editor Intermediate Techniques.
Virtuoso Analog Design Environment Verifier 16.7
Learn learn to perform requirements-driven analog verification using the Virtuoso ADE Verifier tool.
Exchange ideas, news, technical information, and best practices.
The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information.
It's not all about the technlogy. Here we exchange ideas on the Cadence Academic Network and other subjects of general interest.
Cadence is a leading provider of system design tools, software, IP, and services.
Back in January, I posted a Five-Minute Tutorial about creating EM Model files. We'll be referencing this previous post a lot, so check it out quickly right now.
That method has worked well for me, but on my most recent project, I hit some snags. As process nodes evolve, the EM models are becoming more complex, and translation scripts are not able to handle all of the cases. So, I had to dig back in and find a new way to get my EM analysis done. I wanted to share this with everyone, since you are likely to hit the same snags that I did, eventually.
Let's assume this is the first time you're trying to create an EM model file for this process. It's worth checking first if your qrcTechFile already contains em_model info:
>Techgen -process_out qrcTechFile
This will result in a human-readable RCGEN.ict file, from which you can then search for the em_model keyword. If the EM info is there, you can go ahead and just use your qrcTechFile by setting the following two switches in your set_rail_analysis_mode command:
set_rail_analysis_mode -process_techgen_em_rules true -extraction_tech_file qrcTechFile
However, I've yet to see a qrcTechFile that included the EM model info, so let's press on. If the EM info was not there, you can create a qrcTechFile that contains the EM info, as long as you have the .ircx file mentioned in the script method from the previous post (keep in mind that this method only applies to TSMC). You'll need to do the first step in the script method, which is to use the ircxtoict script (located in your extraction installation hierarchy) to generate an .ict file:
>/apps/PVE111/11.11.238/bin/ircxtoict -i IRCX_28NM_8M_typical.ict IRCX_28NM_8M_typical.ircx
This file is human-readable and you can check that it has the em_model info.
Next, you will update your qrcTechFile. I recommend making a separate copy to be used just for power analysis, so that we don't inadvertently mess up anything to do with timing. I use the typical RC corner in my examples, but make sure you are using the right one for your flow.
>cp /proj/yourProj/libs/EXTRACTION/typical/qrcTechFile /proj/yourProj/libs/POWER/qrcTechFile.typical
Now use the Techgen utility to update the qrcTechFile with the .ict file previously created (if you have QRC, you should have Techgen in the same install directory):
>Techgen –update_process /proj/yourProj/libs/POWER/qrcTechFile.typical RC_IRCX_CLN28HPM_1P8M+ALRDL_5X2Z_typical.ict
However, you may have some trouble with an error message about layer names or different numbers of sub-vias. Here is how I worked around that:
I dumped out an ict file of my qrcTechfile with:
>Techgen -process_out /proj/yourProj/libs/POWER/qrcTechFile.typical
This spits out a file called RCGEN.ict. I then copied the em_model sections for each metal and via layer from my RC_IRCX_CLN28HPM_1P8M+ALRDL_5X2Z_typical.ict to the RCGEN.ict file just created. I also had to copy some em_* variables from the top of the file.
Finally, I updated a copy of my qrcTechFile with this RCGEN.ict file:
>Techgen –update_process /proj/yourProj/libs/POWER/qrcTechFile.typical RCGEN.ict
The set_rail_analysis_mode options are still needed, and make sure that you don't have the -em_model_file switch in the set_rail_analysis_mode command:
set_rail_analysis_mode -process_techgen_em_rules true -extraction_tech_file /proj/yourProj/libs/POWER/qrcTechFile.typical
Whew! I know that was a lot to take in, but hopefully it will help you navigate the world of EM Model File creation.
- Kari Summers