Digital Implementation Blogs

Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff in Digital Implementation.
The smaller nodes - let me pick a random small node as an example - 28nm and below - might require newer timing signoff strategies like path-based verification, statistical on-chip variation, waveform propagation, and statistical timing analysis.
The Tempus Timing Signoff and Closure with Stylus UI and Tempus Timing Analysis classes talk about such strategies.
But, before taking those classes you might consider a refresher of the basics of static timing analysis via the Basic Static Timing Analysis course.

Or even slightly faster through these direct videos (if you know what you are looking for):

• Introduction to STA (Video) - In this module, you will identify where Static Timing Analysis (STA) fits into the flow. Identify timing library information for timing arcs in a design, such as unateness, cell delays and net delays, and slew.
• Cell Delay (Video) -In this module, you will identify cell delay information from the libraries Use Table Lookup (TLU) models to calculate cell delay.
• Net Delay (Video) -  In this module, you will apply wire-load models to calculate net delays Identify the file formats used in back-annotation.
• Introduction to Clocks (Video)- In this module, you will identify and apply clock period and pulse width; Calculate the duty cycle of a clock; Identify clock slew or clock transition, identify clock uncertainty, clock latency.
• Timing Checks (Video) - In this module, you will identify the setup and hold information from libraries, and identify how setup and hold times affects timing through flops.
• Timing Paths (Video) - In this module, you will identify the types of timing paths, calculate slack for every path type, and determine the worst timing path in a small circuit.
• Introduction to SDC Timing Constraints (Video) - In this module, you will identify constraints on each type of design object.
• Introduction to STA Timing Reports and Analysis (Video) - In this module, you will identify the essential parts of a timing report, identify some timing analysis strategies, and analyze timing reports.

We have adopted technology to create these videos as well.
Allow me to explain.
I have had trouble in the not so distant past 2012 -feels so long ago, finding the perfect microphones; and then those bad microphones caught my every breath into the audio files, thus causing discomfort to many ears (although that was not my intent  - or was it? Muahaha); And I had also troubled the listener by not being able to properly level the audio from one slide to another, and when I did; I accidentally clipped the audio at a few pl8*es (What was that he said? ). 
But now, I have adopted Artificial Intelligence technology - to take me out of the equation and by using the voice generated via Google® Wavenet and we have created a more consistent experience for you. Voila!

Be a gentle judge and leave your comments of how this might have helped you achieve your learning goals, especially if you were one of my past victims.
Hope you have a joyful learning experience.