Accelerate Design Signoff with the Updated Cadence Voltus Training Kit

20 Jul 2026 • 8 minute read

By Ronen Stilkol, Senior AE Architect

As advanced-node and 3D-IC designs push higher performance into tighter power, thermal, and packaging constraints, engineers must understand how the die, package, board, activity profile, and implementation flow interact. In this environment, signoff success depends not only on powerful tools but also on a guided methodology that shows what to run, why it matters, how to debug issues, and how to apply proven flows to real designs.

That is where the updated Cadence Voltus Training Kit comes in. The latest June 2026 release expands the kit from a training resource into a comprehensive methodology environment for power integrity and signal integrity(SI/PI) and signoff. With more than 170 ready-to-run Rapid Adoption Kits, updated documentation, make-based automation, design-review templates, and an early interactive assistant, the kit helps engineers ramp faster, run flows more consistently, and move from learning to signoff with greater confidence.

The goal is straightforward: turn complex signoff methodology into a practical, guided path that engineers can learn, trust, and apply.

Voltus Training Kit: A Methodology, Not Just a Collection of Examples

The Voltus Training Kit is a Voltus PI/SI signoff methodology integrated into a CAD environment. It uses recommended Cadence PV scripts and settings, TSMC PVT tables, and Self-Heat guides, and it is tested with the latest Cadence tools release and the previous year’s release. The kit is designed for training, customer design, ramp-up and evaluation, QA, test-case creation, and proof-of-concept work for new technologies.

A key design goal is accessibility. Users do not need prior knowledge to start. They download the kit from the Cadence ASK portal, untar it, set the environment, and use make commands to run simulations, read results, view scripts, open documentation, and check errors. This make-based structure helps users focus on the methodology rather than rebuilding scripts from scratch.

The kit supports DP/XP and Common_UI/Legacy modes, with DP mode planned to become obsolete in a future release. It also includes integrated simulation guides, debug documents, design-review templates, and direct document links, so engineers can work in a complete, guided environment rather than searching through disconnected material.

What Is New in the June 2026 Release

The latest release focuses on two major engineering needs that repeatedly come up in customer and field discussions: die/package co-verification and faster access to methodology knowledge.

Stronger Die/Package Co-verification

One of the biggest updates is the expanded package and die-model flow. In practice, die and package teams often need to collaborate, but each side may not fully understand the other's data, extraction steps, or simulation expectations. The updated Voltus Training Kit helps bridge that gap by explaining both directions of co-verification:

Package-to-die: generate a package model and use it in die simulation so the silicon-side analysis can account for the package effect.
Die-to-package: create a die model from Voltus simulation data and provide it to the package design team so the package team can understand current consumption and plan the package more effectively.

This is especially important because package-aware analysis is no longer an isolated activity. Power integrity depends on how the die, package, board, voltage regulator, and design activity interact. The updated kit gives engineers a guided way to understand those interactions and run the flow step by step.

A More Complete Package SPA and Die-Model Workflow

The package SPA section now covers package design using Allegro APD, package extraction using XtractIM, MCP (Mode Connection Protocol) use in Voltus package simulation, and PowerDC package IR simulation in Voltus. The updated package flow shows how to design, extract, and simulate a package using Cadence tools in both batch and GUI-oriented workflows.

Die Model has also been enhanced with die-model transient simulation, die-model frequency simulation, RC and frequency text reporting, and SystemPI die-model simulation with the package model. This helps the silicon and package teams exchange the right information and analyze behavior across frequency-dependent model data.

Interactive Assistant Bot

The June 2026 release also introduces a first-draft Voltus Training Kit interactive assistant bot, launched with make BOT. The bot is designed to help users ask practical questions about the kit, for example, how to run a static simulation, how to access methodology information, how to review environment settings, or how to find guidance on thermal simulation. This is an early version and will be improved over time based on usage and feedback.

The bot reflects a larger direction for the kit: using AI carefully and controllably to improve engineering productivity. In the latest development work, AI was used to help test and improve scripts, support documentation updates, generate question-and-answer coverage from the kit documentation, and assist with automation. The goal is not to replace engineering judgment; it is to help engineers find the right information faster, run flows more consistently, and spend more time solving design problems.

A Systematic Signoff Methodology

The Voltus Training Kit is built around a stage-by-stage signoff methodology for early detection of design power-grid weaknesses, higher failure coverage, and faster root-cause analysis. The recommended flow includes:

Design and library input checks: identify missing vias, shorts, unconnected devices and wires, and library-input issues before they become expensive signoff problems.
Design power-grid weakness checks: evaluate PDN hookup quality of instances.
Static simulation: verify that the power-grid metal density can supply the design’s average current requirements.
Dynamic vectorless simulation: detect design weaknesses with high coverage using smart toggling-instance selection.
Dynamic SCAN simulation: evaluate maximum peak demand current.
Dynamic RTL VCD simulation: use real activity values with state propagation.
Dynamic gate-level true-timing simulation: Use gate-level VCD with true timing for accurate activity and toggle-time simulation, supporting silicon correlation.

Passing the vectorless stage may be sufficient for signoff, while VCD availability improves the correctness of the activity. Dynamic simulation also adds important context by capturing the effect of package and decaps, checking simultaneous switching, and analyzing noise injected by the die, board, and package.

Getting Started with the June 2026 Kit

The setup remains intentionally simple. After downloading the release from the Cadence ASK portal, users can install and launch the environment with the following flow:

cd <your_work_area>
gtar -zxvf VTK_Jun_15_2026.tar.gz
cd VTK_Jun_15_2026/Voltus_Training_Kit
# Edit environment_settings to set the PDF reader, for example: setenv PDF_READER evince
# Source the environment and run make commands
source environment_settings

You may find various common make commands in the Voltus Training Kit.

Bring Your Design into the Flow

The Voltus Training Kit is not limited to canned examples. It can also run user-design simulations using integrated scripts. The June 2026 introduction describes separate paths for Voltus and Insight flows.

Voltus Flow

Download and install the kit from Cadence ASK.
Run make REQUIRED_VOLTUS_DESIGN_INPUTS to identify required design inputs.
Run make ADD_VOLTUS_DESIGN to add the design to the training-kit structure.
Update the block setup file manually if needed.
Source environment_settings and run make commands, such as make RLRP.

The user may further refer to the included design-review presentation in the Voltus training kit for more details.

Insight Flow

Download and install the kit from Cadence ASK.
Run make REQUIRED_INSIGHT_DESIGN_INPUTS to identify required design inputs.
Run make ADD_INSIGHT_DESIGN to add the design to the training-kit structure.
Update the block setup file manually if needed.
Run make commands, such as make INSIGHT_POST_CTS_RPG.
Use the included design-review presentation.

Direct Access to the Full Learning Path

The kit also provides direct links to its documentation so users can go directly to the topic they need. The documentation includes infrastructure guides, design-review templates, and simulation guides for IR basics, Data input preparation, Design input, and Libraries checks, RLRP simulation, Static Simulation, Dynamic Simulation, Power-up Simulation, Die model, Thermal simulations, Signal EM, ESD, Hierarchy Simulation, IR Aware Timing, 3DIC, Package SPA, SoC with Analog Design, Insight and Table2IR to expedite the design as user need not to open the tar gzipped file".

This structure matters because not every engineer needs to learn the complete kit at once. A package engineer may start with Package SPA. A thermal engineer may start with thermal simulation. A digital implementation engineer may start with Insight or IR-aware timing. The full kit remains comprehensive, while individual chapters make it easier for users to learn and apply the methodology that maps to their immediate design challenge.

Why AI Matters in the Voltus Training Kit Evolution

The June 2026 release also shows how AI can improve engineering productivity when used with control and review. In the recent development cycle, AI assisted with script improvements, documentation consistency, bot question coverage, and automation tasks such as generating and updating presentation content from simulation runs. The important principle is that engineers remain in control: AI helps accelerate repetitive or knowledge-search tasks, while engineers validate the methodology and results.

This is where the Voltus Training Kit can become valuable beyond external customer enablement. It can also help internal application engineers, product engineers, and support teams reuse proven flows, learn faster from existing methodology, and respond more consistently to customer questions.

From Tool Knowledge to Signoff Confidence

Power integrity and signal integrity and signoff issues require a structured methodology, correct data preparation, trusted scripts, simulation coverage, debug guidance, and the ability to connect die, package, board, thermal, timing, and analog/digital considerations. The Cadence Voltus Training Kit brings these elements together into a single guided environment. For engineers working on advanced designs, the value is practical: faster ramp-up, more consistent methodology, easier debug, broader simulation coverage, and a clearer path from learning to production signoff.

Download the Cadence Voltus Training Kit from the Cadence ASK portal and explore how the latest release can help accelerate your next design signoff journey. For more information, visit the Cadence ASK portal or contact the support team for guidance on using the Voltus Training Kit.

Power grid weaknesses can appear as IR drop violations, excessive supply noise, timing degradation, or silicon correlation gaps late in the design cycle. In the next blog, we will cover a structured Power Grid Verification Flow Methodology that helps detect weaknesses early, improves analysis coverage, and reduces root-cause debug effort by moving from structural input checks through static simulation and advanced dynamic analysis.