Cadence and Very Cool Stuff

One of the very cool things about my job is that I get to see all kinds of new stuff early. I’m privileged to be involved in technology roll outs, and so get to be involved in early discussions with R&D, Product Engineering, and Marketing. And, I gotta tell you, there is very cool stuff coming out.

As I think we’ve established, I’m a geek. (And there’s my daughter again, rolling her eyes, and saying, “tell’em something they don’t already know, Dad.”) And so when I get a chance to see some of the new stuff being prepped by our R&D teams, I get pretty excited.

Here’s just one thing that’s on the burner – a method to explore the power solution space. I met a good customer today, and he very accurately pointed out that Power Shut Off (PSO) is a system function. The system designers very clearly know what blocks can be shut off when – it is a system function. But Multi-Supply Voltage (MSV) is another matter. Fundamentally MSV is about trading off speed for power – the faster you need it, the more power you’ll need. And this really means that any effective power estimation solution needs to consider the libraries, architecture, and expected implementation. If you don’t consider these, you’re not looking at the full picture. In the absence of the ability to estimate the impacts of timing, any kind of architectural analysis is largely meaningless. I mean, why not set the voltage on everything to 0.1v? You’ll save a ton of power. Of course timing closure might be a bit challenging.

So we’re getting ready to come out with something that will allow exploration of the power solution space; something that will really allow you to trade off speed for power. You set up the starting points – stuff like the libraries, constraints, and the like. You then set up the bounding conditions – the allowed solution space. The tool will then go off and run through the scenarios, identifying the best combination of voltages that will meet your timing and power targets. Under the hood, the tool is taking advantage of RTL Compiler’s target setting function to identify whether a given scenario will meet the requirements.

This will take the guess work out of MSV designs. What I really like is that this is the same technology that will then produce a production quality netlist. So correlation is not an issue – there’s no magic library conversions or RTL manipulations to produce this. You pour RTL, libraries, and constraints in, and you get the right scenario out. And you can then just push the button to implement the scenario.

As I mentioned, I was at a customer today. With me were two members of the R&D team – both PhDs and both widely known in the industry. We were presenting the challenges of low power design and how Cadence flows and methodologies solve those challenges. Now these are seriously smart people, and to see their passion and enthusiasm for the technology was contagious. These R&D guys really know their stuff, and they’re committed to making my customer successful. Cadence has (obviously) being going through a down cycle. But with guys like these, and with the technology we’ve got, no one should count us out. Nor should anyone discount our commitment to our customer’s success. We still have the best flows and tools and technology, and we’re still driving the innovation in the industry. We’ve not changed our passion or commitment one little bit – and don’t let anyone tell you differently.

Oh, and here’s a chance for you to hear about the latest innovations in the Front End Design space: Cadence is hosting the annual FED Event in San Jose on Nov 10. This is an event with R&D leaders discussing the new technology and innovations coming out in the next releases. You’ll hear from all of the R&D leaders in this space, and hear from other customers using our technology. And you’ll even get to see me – I’m on a panel offering my perspective about FED. Sign up at www.secure-register.net/cadence/ld_event2009 and I hope to see you there.

Rich Owen