• Home
  • :
  • Community
  • :
  • Blogs
  • :
  • Digital Implementation
  • :
  • Cadence: Committed to DFM

Digital Implementation Blogs

  • Subscriptions

    Never miss a story from Digital Implementation. Subscribe for in-depth analysis and articles.

    Subscribe by email
  • More
  • Cancel
  • All Blog Categories
  • Breakfast Bytes
  • Cadence Academic Network
  • Cadence Support
  • Computational Fluid Dynamics
  • CFD(数値流体力学)
  • 中文技术专区
  • Custom IC Design
  • カスタムIC/ミックスシグナル
  • 定制IC芯片设计
  • Digital Implementation
  • Functional Verification
  • IC Packaging and SiP Design
  • In-Design Analysis
    • In-Design Analysis
    • Electromagnetic Analysis
    • Thermal Analysis
    • Signal and Power Integrity Analysis
    • RF/Microwave Design and Analysis
  • Life at Cadence
  • Mixed-Signal Design
  • PCB Design
  • PCB設計/ICパッケージ設計
  • PCB、IC封装:设计与仿真分析
  • PCB解析/ICパッケージ解析
  • RF Design
  • RF /マイクロ波設計
  • Signal and Power Integrity (PCB/IC Packaging)
  • Silicon Signoff
  • Solutions
  • Spotlight Taiwan
  • System Design and Verification
  • Tensilica and Design IP
  • The India Circuit
  • Whiteboard Wednesdays
  • Archive
    • Cadence on the Beat
    • Industry Insights
    • Logic Design
    • Low Power
    • The Design Chronicles
Manoj Chacko
Manoj Chacko
19 Jun 2009

Cadence: Committed to DFM

On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions. A few of the published items do not accurately describe the actions that were taken, and we’d like to set the record straight.

Manufacturing-side DFM involves post-tapeout processing that transitions a finished layout into the factory (i.e. for manufacturing). Cadence has successful offerings in this area and will continue to appropriately invest. But in select areas such as mask proximity correction our investment will decrease as we emphasize design-side DFM.

Design-side DFM means seamless incorporation of manufacturing process effects within the design environment – like the Cadence Encounter® Digital Implementation System and Cadence Virtuoso® custom design environment – so designers can implement manufacturing-friendly designs that achieve higher yield and performance while meeting tight design schedules.

Our design-side DFM tools, including Cadence Litho Physical Analyzer (LPA), Cadence Litho Electrical Analyzer (LEA), Cadence Chemical-Mechanical Polishing (CCP) Predictor, and Cadence Pattern Analyzer (CPA), are production proven at multiple technology nodes. The Cadence LPA, for example, was the first tool qualified by TSMC from 90nm through the advanced nodes. The Cadence LEA is the first of its kind in the EDA industry. And the Cadence CCP is the established CMP predictor tool used by most leading foundries and IC manufacturers.

Today most of the top 20 semiconductor companies use Cadence design-side DFM tools. Leading semiconductor companies like TI, Freescale, AMD, Broadcom, Qualcomm, TSMC, Chartered, UMC, NXP, NEC and others have publicly described the successes they have had with our tools and technology in published papers. Cadence continues to develop and integrate DFM technology to address next-generation manufacturing requirements, such as double patterning. We hope this perspective clears up any confusion generated by speculative blogs. Cadence is committed to DFM.

Manoj Chacko

Tags:
  • Advanced Node |
  • Mixed-Signal |
  • encounter |
  • Virtuoso |
  • Manufacturability sign-off |
  • Digital Implementation |
  • DFM |