How Do You Solve a Problem Like Clock Tree Synthesis?

Clocks for measuring time are one of the oldest inventions. Timekeeping has advanced from sundials and hourglasses to the world’s most accurate clock, which happens to be in the United States. The National Institute of Technology built the clock, and it is reportedly so precise that it does not lose even a second over the entire age of the universe. Just as clocks are central to modern life, clock trees are central to digital design implementation. Synthesizing and optimizing clock trees is one of the biggest challenges in implementation. If not optimized, the clock network can dissipate up to 30% -40% of your design’s power and contribute to missing your design’s PPA targets.

The Clock Concurrent Optimization (CCOpt) technology in Innovus merges timing optimization with clock tree synthesis, thus converging your PPA requirements faster. The CCOpt tool also leverages useful skew for timing optimization and includes a visual debugger that helps you pinpoint violations. This video on the Cadence Support site illustrates how to use the clock tree debugger. To learn more about how to use the CCOpt tool to achieve the best results, register for the course Innovus Clock Concurrent Optimization with Stylus Common UI.

After completing the course, you will be able to:

• Implement the clock tree using CCOpt technology using the generated constraints
• Specify clock properties to customize the clock tree, including:
  • Defining route types, CTS cells, stop and ignore pins
  • Modifying source latency settings in hierarchical implementation to meet timing at the block level
• Analyze and debug the tree using the information in the log file
• Analyze the QoR of the generated tree
• Assess how CCOpt analyzes chains between register stages, and
  • Recognize when CCOpt uses slack in chains to meet timing
  • Review the log file and determine how the worst chain analysis report can provide additional information about why the timing could not be met.
• Run the Clock Tree Debugger in trial and cluster modes of CCOpt to determine causes for unmet clock targets.
• Evaluate the advantages and disadvantages of various clock structures
• Implement a flexible H-tree

After completing the course, you can take the exam, and when you pass the exam, you will receive a badge that you can display on social media.

Happy Learning!

Vinita