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Vinod Khera
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What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?

22 Aug 2022 • 3 minute read

Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves Transformative PPA and Improved Productivity

The semiconductor industry is in the midst of a global renaissance. With the advent of technologies like 5G, autonomous driving, hyperscale compute, and the Internet of things, there has been an explosion in demand for electronics. Consumers want chips that must have more functionality, more compute, and faster data transmission speed. But these complex chips must also be produced faster to keep up with the increasing demand.

So, to stay ahead of the competition and meet the increasing demand, design companies must produce chips with better PPA and find new ways to improve productivity. This has been made possible by an AI-enabled chip optimization solution – Cadence Cerebrus.

This Intelligent Design Explorer is a transformational ML-based technology with a unique reinforcement learning engine, which optimizes the chip design options to deliver improved PPA beyond human potential with significantly less engineering effort and overall time to tapeout.

The proof is in the pudding. In the recent CadenceLIVE Silicon Valley 2022, Tony Han, Director of MediaTek, spoke about leveraging Cadence Cerebrus solution in their design flow, enabling them to shrink the die size by 5% and lowering total power by more than 12% on a critical macro. Using Machine Learning Model also reduced overall optimization time from 18 days to 8.3days, significantly improving engineering productivity.

"At MediaTek, we are resolute in delivering optimal PPA, making the Cadence Cerebrus AI-based solution the most logical choice for our latest, advanced-node projects," - Harrison Hsieh, MediaTek. 

Key Cerebrus Features that Led MediaTek to Deploy Cerebrus in Production flow 

After integrating Cadence Cerebrus, MediaTek observed a considerable PPA boost, productivity improvements, and smaller die by enabling the Cerebrus Floorplan Optimization App.

Improved Total Power 

While moving from baseline flow to Cerebrus optimized flow on a critical macro, MediaTek observed 26.3% improved Total Negative Slack and 9.6% improved Total Power. After instantiating this macro inside an IP, the Fmax was improved by 150MHz, along with a 12.5% reduction in Total Power.

Phenomenal Productivity improvement

Once Cadence Cerebrus is run on Early RTL, it generates a Machine Learning Model, which can then be reused by the newer release of the same RTL or similar designs to transfer the intelligence captured from the previous run. This helps the engineering teams to reduce overall optimization cycle time and use compute resources efficiently. MediaTek made use of this feature, helping them reduce the design time from 18 days down to 8.3 days, improving run time productivity by 53.88% 

Floorplan Optimization Cerebrus App

MediaTek used the Floorplan Optimization Cerebrus App to optimize the die size. With the increasing complexity of designs, it's impossible to manually optimize the macro placement, die size, core shape, and other aspects of the floorplan. Using ML-based optimization, Cerebrus can explore the most optimal solution space, which otherwise would not have been possible. They achieved up to 6% improvement.                                   

Ease of Integration: Cadence Cerebrus Adoption into MediaTek Production Flow

Cadence Cerebrus is easy to adopt because it easily wraps around any custom flow without requiring a significant overhaul of the current chip design flow. As a result, it was easy for MediaTek to port their existing full flow using Genus, Innovus, and Tempus into the Cerebrus environment for production use. This methodology also keeps the baseline flow intact, allowing comparisons of various metrics generated during multiple iterations.

Conclusion

Cadence Cerebrus Optimization Solution helped MediaTek achieve better PPA and Productivity. They saw a reduction of 12.5% in Total Power on a critical macro, a die size reduction of 5%, and productivity improvement of over 53%. All this and ease of adoption led them to deploy Cerebrus for production use on a wide scale across the company.

Learn More

  • Cadence Cerebrus AI-Based Solution Delivers Transformative Results on Next-Generation Customer Designs
  • Cadence Cerebrus Intelligent Chip Explorer
  • Cadence Extends Digital Design Leadership with Revolutionary ML-based Cerebrus,   Delivering Best-in-class Productivity and Quality of Results
  • Cadence White Paper: Machine Learning-Driven Full-Flow Chip
  • Design Automation

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