Low-Power Equivalence Checking in Modern SoC Flows

Background: Why Low-Power Equivalence Checking?

In modern SoC design, advanced low-power techniques such as dynamic voltage and frequency scaling, fine-grained power gating, multiple voltage domains, and state retention introduce additional logic and complexity to the chip. Unified Power Format (UPF) or Common Power Format (CPF) files are used to capture the design's "power intent"—describing power domains, power states, special cells (isolation gates, level shifters, retention registers), and required supply conditions.

These power-intent files guide EDA tools to automatically insert low-power structures into the netlist during synthesis and implementation, ensuring that circuits can safely power down or change voltage levels while preserving data or clamping signals. While essential, this process transforms the netlist beyond the plain RTL behavior, raising the question: is the low-power-augmented gate-level design still functionally equivalent to the original RTL?

Traditional verification alone (e.g., simulating the design with power-emulation models) is insufficient to thoroughly validate low-power behavior. Full-chip gate-level simulations with power shut-off scenarios are extremely slow and often impractical for large designs. Instead, formal equivalence checking augmented for low power provides an exhaustive and faster approach.

Cadence's solution—Conformal Low Power (CLP)—addresses this need by performing static structural and functional checks specifically for power-managed designs. It verifies that the power intent (from UPF/CPF) is correctly implemented and that no erroneous logic or mismatches have been introduced by adding power controllers and low-power cells.

In general, LPEC tools like Cadence Conformal Low Power solve two key problems in modern flows: firstly, checking direct equivalence between a golden design (RTL or pre-power-optimized netlist) and a revised netlist that includes all power-management modifications (power-gating logic, inserted isolation/level shifter cells, etc.). This power-aware equivalence checking ensures the design's functional behavior remains unchanged in active (powered-up) states. Secondly, Conformal Low Power performs static rule checks to flag structural issues, such as missing or incorrectly connected isolation cells or retention control pins, as well as any inconsistencies between the power intent specification and the design implementation. By catching these errors early, Conformal Low Power reduces the risk of latent low-power bugs causing functional failures or silicon respins.

Cadence Low-Power Equivalence Checking Solution

• LP Verify — Static Signoff Checks: 600+ static LP checks from RTL through P&R, electrical/leakage checks for LP cells, power-intent quality/syntax validation, advanced LP cell support, and Tcl waiver/filtering.
• LP Compare — Two-Design Consistency: Power intent, power grid/supply set, PST, crossing, and Liberty-vs-UPF consistency comparisons.
• LP-EC — Power-Aware Equivalence: Logic equivalence with virtual ISO insertion, ISO/RET/PSW control signal comparison, virtual logic connection per power intent, and PSW acknowledge signal checks.

Usage of Cadence LPEC

Many semiconductor teams utilize Cadence's low-power equivalence checking at critical verification milestones.

A common practice is to run Conformal Low Power at the end of the design flow as part of final verification signoff, comparing the fully implemented gate-level netlist (with inserted power-management logic) against a golden RTL or gate-level model without those power optimizations.

By doing so as a mandatory step before tapeout, teams catch any inadvertent functional divergences caused by low-power structures that might not have been caught during standard verification.

This signoff usage aligns with industry recognition that low-power verification needs a formal signoff step similar to timing or functional signoff.

However, more advanced users incorporate Conformal Low Power earlier in the flow as well, rather than waiting until the very end.

Mature flows use CLP at multiple design stages (pre-synthesis, post-synthesis, and post-layout) as a layered defense against low-power bugs.

Customers also leverage CLP's diagnostics to debug issues when an equivalence mismatch is found.

What Is Lacking in Current Low-Power Verification Processes

Despite the availability of static low-power verification tools like Conformal Low Power, many teams do not fully exploit them. Common gaps observed in current customer processes include:

• Applying low-power equivalence checking late in the flow rather than progressively. Many projects only run Conformal Low Power as a final step. This means if a logic bug was introduced by power optimizations (for example, an isolation cell clamping a signal erroneously), it may only be caught at the very end, causing late rework. Without early checks, some low-power mistakes remain hidden until final signoff.
• Limited coverage of power modes and corner cases. Often the formal equivalence checks are done only for the "all power domains on" state (to ensure the active-mode logic is preserved), but not all combinations of power states are considered. Some flows may not verify behaviors during transitions (powering domains on/off) except via simulation, which might not exhaustively cover all sequences. These coverage gaps leave risk that certain power-down modes or recovery sequences aren't fully validated.

Recommended Improvements to LPEC Methodology

To address the above gaps, the following improvements are recommended for teams using Cadence's low-power equivalence checking. These suggestions aim to ensure more thorough coverage, earlier bug detection, and smoother integration of CLP into the overall verification process:

• Incorporate CLP at multiple stages of the design flow: Run an initial static power intent consistency check once the UPF/CPF is written (to preempt structural mistakes).
• Perform an RTL-to-synthesis equivalence check after logic synthesis and after insertion of low-power structures, rather than waiting till the end.
• Finally, perform full-chip CLP at P&R signoff as a last line of defense. This multi-pass approach catches issues as early as possible, when fixes are less disruptive.
• Define metrics and a signoff checklist: Create explicit low-power verification signoff criteria. A structured checklist can formalize that the design has undergone thorough low-power verification before tape-out.

Utilize Unified User Interface for Fast Debug

• Easy Diagnosis — LP Debug Manager, Power Intent Viewer, Domain Crossing Viewer, and PST Viewer for clear visualization.
• 100X+ faster PST analysis enables early-stage validation without a full netlist and supports AI diagnosis on project history.
• Root Cause Analysis auto-groups related violations by common cause and suggests fix actions.
• Multi-threading delivers scalable performance with minimal memory overhead.
• Distributed hierarchical flows (top-down, bottom-up, block-in-SoC-context) match flat full-chip results with automatic CPU/machine partitioning.

Conclusion

By systematically applying low-power equivalence checking with Cadence Conformal Low Power throughout the design cycle, verification teams can significantly reduce the risk of power-related functional bugs reaching silicon. Conformal Low Power formal approach provides exhaustive coverage of low-power scenarios and catches subtle errors that might slip past simulation. While many customers already leverage CLP for signoff, expanding its use earlier and refining processes around it will improve coverage and confidence in low-power designs. The improvements outlined in this report—from early integration to explicit verification metrics—will help organizations achieve robust low-power signoff and ultimately contribute to first-pass silicon success for power-efficient SoCs.