Constraint Construction: What's Its Function? Part 3 of 4

Part 3. EXCEPTION PATHS: For Every Rule, There Is An Exception

More often than not, I'll start an optimization on a block only to have it result in thousands of timing violations.  Many times, the culprit is a missing path exception constraint.   When you see timing violations that are suspicious, ask the RTL/constraint developer whether there are exceptions to the timing rules you're trying to meet. Let's go over some items to consider when debugging timing!

• Multi-Cycle
  • (set_multicycle_path)
  • Are certain paths allowed more than one clock cycle? 
  • Have these been properly defined for BOTH setup and hold?

"So my setup violation went away, but now I have -2ns hold violation.  Come on, that can't be real?!"

• False Paths
  
  • (set_false_path)
  • Are there asynchronous paths, or ones that no timing is necessary? 
  • Are you sure that wildcard '*' is being applied correctly in this case?

"Finally, a constraint I can use:  set_false_path -from * -to *"

• Path Delay
  
  • (set_min_delay/set_max_delay)
  • Is there a minimum or maximum amount of time a path should take?

"So you'd like me to work with a path delay between 1.000ns to 1.001ns in all corners.  Let me just put my blind fold on and tie this hand behind my back, cause you're about to see some magic..."

• Constants
  
  • (set_case_analysis)
  • Are there any ports or the output of a flop that sets the functional or test mode of the constraints?

• Dont Care Paths
  
  • (set_disable_timing)
  • Are there paths that no data or clock should pass through?

"Then I disabled the timing arc on this clock gate and all my problems went away"

• Dont Touch Paths
  
  • (set_dont_touch)
  • Are there areas that should be left alone by any optimizer? 
  • Will the optimizer touch that ring oscillator?

"Good news!  I reduced that ring oscillator thingy you guys added in down to a single inverter.  Yeah, I know, you can thank me later."

• Dont Use Cells
  
  • (set_dont_use)
  • Are there any cells you're not allowed to optimize with? 
  • Did the synthesis team follow those rules too?

"Well they were using these cells so I figured I could too..."

It seems like when the physical designer is desperate to meet a timing path, we tend to pray that there is a false path or multicycle path available to us.  But it can often be difficult for the constraint designer to catch these up front.  When that's the case, try looking into the Conformal Constraint Designer (CCD) which can be launched through Encounter.  It can be used to catch these path exceptions early on!

Next up in the last segment of this series we'll discuss Design Rules and Modes of Operation.  See you then!