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Are you passionate about cooking? Err... Don't think it is a regular cooking class.
Here we tend to cook cooler power solutions!
Do you know creating a cooler IC chip is as easy as enjoying the ice-cream in summer to beat the heat?
Low-Power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power.
Well, the ingredients for the recipe could vary based on your design and specifications.
Is it a regular low-power flow?
Are you using multiple supply voltage (MSV) design, power shutoff (PSO) synthesis, and dynamic voltage frequency scaling (DVFS) synthesis techniques in the form of the IEEE 1801 power intent file?
In this cooking session, you will be:
We understand that it is not always easy to estimate power, but we can guide you!
There is a ONE-STOP session to all these requirements in the form of the training course on "Genus Low-Power Synthesis Flow with IEEE 1801 v21.1 (Online)".
Course Title: Genus Low-Power Synthesis Flow with IEEE 1801
Enhance the Genus Synthesis experience with videos: Genus Synthesis Solution: Video Library