Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs.

For the majority of ASIC designs, signoff analysis includes executing parasitic extraction that feeds static timing analysis, signal integrity analysis and power rail IR drop analysis. Most often this is standalone execution using a separate set of tools than those used in design, and the obvious goal of this analysis is to ensure good quality silicon.

What is interesting is that, today, a robust ASIC design methodology must employ the same signoff analysis engines within the design flow, to ensuring that timing is consistently closed and IR drop is consistently managed. This is certainly the case with Cadence’s Encounter Digital Implementation System (aka EDI System), which can utilize all of the signoff engines (parasitic extraction, timing, SI and IR drop) within the design platform.

The use of signoff engines within the design environment opens up an interesting question ... if I am using signoff quality engines within my design flow, is there significant value in performing separate, standalone signoff analysis prior to tapeout?

The answer for an increasing number of my customers is no … separate signoff analysis does not catch any additional and significant timing, SI or IR drop problems. These customers chose to signoff from within the design platform and save the expense of purchasing and maintaining separate standalone signoff products.

So, I have an open question to the design community … what are your thoughts on separate signoff analysis?

Pete