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If you missed joining or registering for the RTL-to-GDSII webinar, the complete recording is now available as a Training Byte at the Cadence support site so that you can watch and explore the complete flow, including the latest features of tools such as Xcelium Logic Simulator, Integrated Metric Center, Genus Synthesis Solution, Cadence Modus DFT Software Solution, Conformal technologies, Innovus Implementation System, and Tempus Timing Solution.
This webinar will teach you the essential steps in the RTL-to-GDSII design flow using Cadence tools. You will explore topics such as writing RTL code using Verilog or VHDL, synthesizing the RTL design into a gate-level netlist, inserting scan chains into the netlist for testing and debugging, performing logic equivalence checking to verify that the synthesized design is functionally equivalent to the original RTL design, implementing the netlist by performing implantation and timing signoff to verify that the design meets all its timing requirements and extracting the GDSII file from the physical layout to manufacture the chip.
This webinar will dive into the following:
Please find the recorded video below, placed as a training byte on the Cadence support site (support.cadence.com). The recording video now features a table of contents that shows the list of topics, and you can click to jump to a specific topic at any time in the complete video.
Learn more about and enroll in the related Cadence RTL-to-GDSII Flow training course. The course includes slides with audio and downloadable laboratory exercises designed to emphasize the topics covered in the lecture. There is also a digital badge available for the training.
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