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been a lot of new faces springing up in the signoff analysis market over the
past few years and the trend seems to be pointing toward products that deliver
quick and reasonably good timing signoff with some signal integrity analysis
tacked on as an afterthought. This prompted me to ask the question: Just how
important is noise analysis accuracy and quality?
this question, I first looked back at the history of noise analysis and how it
evolved from being a nice-to-have security blanket to an integral part of
design closure. To make a long story short: Signal Integrity (SI) analysis
began to catch on in 2000 as 180nm - 130nm design starts increased. 90nm design
starts began to ramp up in 2002 and by 2004, signal integrity analysis hit the
mainstream and was seen as a must-have to ensure reliability while maintaining
design margins. Now enter present day where SI fixing is a regular part of the
design closure loop and a standard offering of all signoff timing solutions.
the rise of SI analysis, it has proven its worth many times over by saving
numerous designs from failing in silicon. This is no small feat and is
accomplished by finding and then fixing functional and timing failures induced
by crosstalk noise during design implementation. In today's world of
cutting-edge low-power design, this means that SI analysis must be able to take
into account the complex signal integrity problems that can come from mixing
Multi-Vt cells, domains with different supply voltages, and new low power cells
such as level-shifters and power gates.
will any SI solution do?
deeper, I found that SI analysis accuracy and quality matters in a big
way. I've recently come across 4 instances in customer evaluations where
the very accurate CeltIC technology in Encounter Timing System found major
noise-induced problems that the others could not catch. When all of these
issues were checked against the golden SPICE simulation, they proved to be
issues that, if left unresolved, would very likely have caused failures in
silicon. Issues such as "Double Clocking", unpredictable accuracy, and delay
pushout optimism were the most common. While some solutions offer impressive
turnaround time at the expense of accuracy, these customers decided that they
weren't ready to take the risk of a re-spin which could cost over $1M at
smaller process nodes.
isn't reason enough to consider SI accuracy, you can also consider that better
accuracy means less pessimism which in-turn results in fewer violations to
resolve in the final stages of design closure. So, based on this, I think it's
reasonable to say that noise analysis accuracy matters in really big way and
that any shortcuts just aren't worth the risk of failing silicon.
what do you think? How important is noise analysis accuracy to you?
Also what are the process nodes (nm wise) at or below which SI analysis is important. is anybody doing SI analysis at 180m,...
When is Cadence going to come out with Package + Die + Functional Vector Annotation based IR Drop Analysis, and associated Crosstalk and Glitch problems..
you will appreciate that the Corner based impedences will be changing drastically once supply voltage dips below a technology specific/ Cell's circuit topology based constraint.
I am eagerly waiting to see such a solution, which in turn will enable more designs in extremely low energy computation.
JohnB & Elvis, Great questions and thank you for taking the time to comment. I'll make that the topic for the next blog entry so stay tuned...
Mike - Thanks for the post. Noise is an issue for sure. Can you elaborate the issue you identified as "Double Clocking" and what you mean regarding "unpredictable accuracy"? Thank you.
Noise is an issue, certainly. I would like to see more specifics (substantiation) on what CeltIC can do that other comparable SI tools cannot.