From Concept to Cool: Optimizing Low-Power Design with Genus Synthesis Solution

Join Cadence Training and Education Application Engineer Architect, Neha Joshi, for this free technical Training Webinar, which will offer a detailed overview of low-power design strategies.

Low-power synthesis isn’t just an IC design flow box to be checked; it's a foundational step and a strategic necessity.

As modern SoCs become more power-sensitive, early power optimization at the synthesis stage becomes critical to achieving design closure without compromising functionality or timing. The Cadence Genus Synthesis Solution focuses on early RTL-level optimizations that influence power, performance, and area (PPA).

Agenda

• Low-Power Design Strategies from Motivation to Implementation
• Refresh: Low-Power Concepts
• How to Write an IEEE 1801 File
• Genus Low-Power Synthesis Flow

Date and Time
Wednesday, October 15
07:00 PDT San Jose/10:00 EDT New York/15:00 BST London/16:00 CEST Berlin/17:00 IDT Jerusalem/19:30 IST Bengaluru (Bangalore)/22:00 CST Beijing

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Genus Low-Power Synthesis Flow with IEEE 1801 Training Course | Cadence

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Related Courses

• Genus Synthesis Solution with Stylus Common UI Training Course | Cadence
• Joules Power Calculator Training Course | Cadence
• Fundamentals of IEEE 1801 Low-Power Specification Format Training Course | Cadence

 Training Bytes

• Exploring Zero-Pin Retention for Low-Power Designs (Video)
• Basic Synthesis Flow in Genus Stylus CUI (Video)
• IEEE 1801 Flow in Genus Stylus Common UI (Video)

 Blogs

• Elevate Your EDA Skills: Achieve Unmatched PPA with Genus Synthesis Solution - Digital Design - Cadence Blogs - Cadence Community

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