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Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen & Krishna, having "perfect correlation" for timing from RTL to Signoff can dramatically improve design closure and cycle time which is always a good thing.
I enjoyed this article because it not only talks about the benefits of making sure you have correlation but goes into great detail on exactly how to ensure it. Check it out on EDN's web page here:
Establishing Timing Correlation Between Tools
One of the keys to is also starting with the right tools. If your flow can leverage common timing and SI engines it makes your job much easier. Learn more about the common timing and SI anaylsis infrastructure in Cadence's Encounter Timing System and Encounter Digital Implementation System.