Get email delivery of the Cadence blog featured here
Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out, and now the HLS community is talking and sharing experiences with each other.
Take CDNLive, for instance. This year, HLS discussions are happening at the CDNLive shows worldwide. Since it’s extremely unlikely any of you have visited both shows in Silicon Valley and Germany, I’ll give you the HLS highlights.
Tuesday afternoon started off with Rajat Dhawan of Qualcomm Technologies, Inc., presenting to an audience of over 50 people. In his presentation, “Design implementation of technology IP using High-Level Synthesis,” Rajat discussed the experiences of their team’s multiple tapeouts with Stratus HLS. He detailed the SystemC-based verification flow, and how HLS dovetails seamlessly into their corporate RTL design and verification flows.
Oh, yeah… and the audience loved the presentation. Based on audience votes, he won the Best Presentation Award for the Front-End Design track, which landed him an iPad Mini. Congratulations, Rajat!
(No, that’s not Rajat. I accepted the award on his behalf… but I didn’t get to keep the iPad Mini!)
In case you missed this presentation at CDNLive, Rajat will also be presenting at the Design Automation Conference (DAC) this year. If you are attending DAC, see him Wednesday at 5:30PM at the Cadence Theater.
Next, Michael (Mac) McNamara of Adapt-IP discussed the flexibility of HLS-based IP design in, “Design and Verification of Low-Power Flexible 802.11ah IP with Stratus HLS.” Mac discussed some of the inherent difficulties when designing baseband IP that need to work with different radios, and how HLS helped to address those challenges.
He also detailed how they reacted to late specification changes. As you may remember from a past blog, this is one of my personal favorite topics… it falls into the category of, “I couldn’t have done THAT by hand!”
Finally, one of our university partners, Dr. Matthew Morrison at University of Mississippi discussed his line of research, including using HLS to develop circuits resistant to differential power analysis (DPA) side-channel attacks. (Image courtesy University of Mississippi)
A month later at the next CDNLive in Munich, Germany (a.k.a. München, Deutschland), Socionext’s Tim Papenfuss discussed the challenges in designing a video decoder, including clock domain crossings (CDC), I/O modeling, and verification. His presentation, “Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS,” is available in the CDNLive proceedings (login required).
Dror Constantinis of Cadence also detailed some of his experience in his 10-year love affair with HLS in his presentation, “So How Can the HLS Flow Help You Cut TTM?” Finally, Marios Karatzias and Dirk Seidler detailed “The Full-Full Flow Low-Power Solution” in their tutorial about creating low power silicon with the Cadence flow.
As I discussed in a recent Semiconductor Engineering article, “low power optimization” means different things to different people. For those who are optimizing for the lowest possible power, that effort must begin in the early system and architectural design phases. HLS links those decisions to the real power, performance, and area (PPA) impact.
Stay tuned to hear about what other Stratus HLS users are talking about worldwide, including at Design Automation Conference (DAC) and future CDNLive’s worldwide.