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Summer is usually a slow time of the year due to vacations, beautiful weather, and backyard barbeques. But for the HLS community, this summer has started off hot.
At the 2015 Design Automation Conference, there was a lot going on with high-level synthesis, both at the Cadence booth and elsewhere. But first, I must say, it was a lot of fun talking to so many people, including current and future users of HLS, and even a few “future users who just don’t know it yet.”
Speaking frankly, last year was a whirlwind for me at DAC, as I was still absorbing what it meant to work for Cadence instead of Forte. This year, with my feet under me, it was actually a lot of fun.
In a Cadence DAC Theater presentation titled, “High-Level Synthesis: A Winning Technology,” Masato Tatsuoka of Socionext detailed how they used HLS to be first to market with a 4K/p60 HEVC video encoder chip. They detailed their use of TLM interface IP, architectural exploration, and a physically-aware HLS flow to achieve first silicon success. This was a very cool and innovative application of HLS, but instead of taking my word for it, check out a video of the presentation yourself.
Tatsuoka-san also presented their paper, “Physically Aware High Level Synthesis Design Flow,” in DAC Paper Session 65, “From Algorithms to Bits,” chaired by Cadence’s own Alex Kondratyev and co-chaired by Frederic Doucet of Qualcomm.
We were also lucky enough to have Marleen Boonen and Dejan Đumić from Methods2Business in the Cadence booth presenting a session titled, “Leveraging a SystemC-Based Design Flow to Realize ULP 802.11ah Wi-Fi™ Hardware and Software IP.” They implemented a comprehensive methodology encompassing hardware, software, and architecture selection and optimization. Again, very innovative. Very cool.
But as I said, not all of the hubbub about HLS at DAC was in the Cadence booth, nor in paper sessions we chaired. For example, Designer and IP Track Poster 31.33 had Elad Litman from Intel presenting, “HLS Soft-IP: The New Standard in Soft-IP Creation.” He quantified the productivity and QoR advantages that Intel has experienced on several different projects, concluding that, “Full-HLS flows show to be especially valuable to repurpose IP for different performance and PPA skews.” In short, using HLS makes the IP you design more valuable. A recurring theme of the summer so far.
A few weeks later, at SystemC Japan 2015, there was another flurry of high-level synthesis activity. Fujitsu Laboratories Limited explained their HLS methodology resulting in a 30% man-hour reduction for development of H.265 IP that was more flexible and extensible than RTL-based IP.
KYOCERA Document Solutions, Inc., long time HLS users, explained how they used they extended their SystemC methodology to architectural exploration by using the object-oriented features of C++. Makes sense…after all, SystemC is just a C++ class library, so you get those benefits, too.
Ricoh Co., Ltd, talked about their experiences in the differences between software and hardware designers, leading to better and more efficient cooperation between them in a hardware flow that starts with a software language (again, SystemC is C++).
Finally, there was a spirited panel discussion titled, “Is SystemC IP really necessary?” with panelists from Adapt-IP, Inc., Socionext, Sony, and Toshiba Information Systems discussing if, when, and how SystemC IP should be created, used, distributed, and licensed. That is very similar to the Intel poster at DAC, but from more of a business end than technical.
And then somewhere in between the haze and thunderstorms of a hot Pittsburgh summer, Brian Bailey and I had a chance to talk about HLS from a pragmatic point of view, discussing some of the ways industrial HLS has overcome the technical difficulties Professor Brewer from UC Santa Barbara had enumerated at the ESLSyn conference.
Brian has a very down-to-earth approach, which is reflected in his conclusion. “At the end of the day, the users have spoken and most of the top semiconductor companies are using HLS. They pushed the EDA vendors into the C, C++, SystemC camp, and they are using HLS to create chips that are making them money. They may not be optimal, but they are probably more optimal than they would have been if an engineer had designed it without help from the tools.”
And that’s proven to be exactly right, with a litany of semiconductor companies like the ones above joining the chorus that HLS helps them create more valuable IP.
One final comment… I mentioned earlier about the whirlwind transition from startup to big company. If anyone out there is thinking about a similar change, here’s one piece of advice for you. Go to a company that is a Great Place to Work! If not, your mileage may vary.