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PeteMc
PeteMc

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VDD
VDD I/O
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IR drop
EM Failures

IR Drop Analysis: It's Not Really Necessary, Is It?

5 Apr 2010 • 2 minute read

I was recently asked by an engineering manager if running IR drop analysis was really necessary. The argument to support his question was that his engineering team always over-designs the power rails, and so the risk of getting high IR drop was so small that analysis was not required.

The easiest way to answer his question was to relate what actually happened during the creation of a DAC demo a number of years ago.

The demo was designed to initially suffer from high IR drop in the center of the design, and the plan was to short the VDD of this region to a solid VDD, and hence fix the high IR drop. Figure 1 shows the initial IR drop analysis results, with the high IR drop in the center of the design. You can also see the solid VDD net just below the red region of IR drop.

 



Figure 1: Initial IR drop plot

 
While the added jumper did help reduce the highest IR drop in the center, it also enabled current to flow through a completely different path from the lower right boundary VDD I/O pad to the center of the design. This new path caused higher currents to flow around a memory, and resulted in new electromigration (EM) failures around the sense-amps of the memory. Figure 2 shows a zoomed in view of the lower right of the design, where you can see the added VDD jumper and the new EM failures.

 



Figure 2: VDD jumper plus new EM problems in lower right memory

 
When we saw this result, it surprised everyone involved and we were all experts with many years of experience in both chip design and IR drop analysis. No-one could have predicted how the addition of a small jumper in the center of the design could have caused new EM problems towards the corner of the design.

That's the reason why power rail analysis is required!

While we would like to believe that we can predict how current flows through the power network, in reality the current often flows unpredictably through multiple levels of interconnect and complex gridded power networks. It is the inability to predict how the current flows that forces the need for analysis.  How can you possibly over-design the power rails when you don't know where, and how much, current is flowing though them?

Anyone have other thoughts on this?

Pete


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