Joules RTL Design Studio: Accelerating Fully Optimized RTL

Cadence announced Joules RTL Design Studio today at CadenceLIVE Japan 2023, a new product that expands upon Cadence’s existing Joules RTL Power Solution. The solution will address all aspects of physical design by adding visibility beyond just power into performance, area, and congestion.

Lack of visibility into early power, performance, area, and congestion (PPAC) metrics is a challenge that has, for the most part, been unsuccessfully addressed. RTL designers face this challenge regularly and, as a result, are unable to quickly debug their source code at a stage where critical timing and congestion problems must be resolved. The ability to perform accurate RTL analyses and intelligent debugging prior to handing the design to the synthesis and physical design teams is necessary for design teams to meet competitive schedules and get differentiated products to market on time. Joules RTL Design Studio’s expert system triages possible causes of violations and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design. Ultimately, the goal is to empower front-end designers with technology that enables fully optimized RTL for implementation handoff and to provide RTL designers with capabilities to assist in the implementation convergence process.

Joules RTL Design Studio features can unlock up to 5X productivity increases and 25% PPA improvements. The solutions PPAC estimates are driven by the core engines from the industry-leading Cadence products Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, so users can trust the accuracy of their design decisions implicitly. The Innovus GigaPlace placement, NanoRoute global routing, Genus iSpatial, and Joules power engines ensure accurate, trusted PPAC estimates that will track with production implementation. Additionally, the Joules RTL Design Studio has tight integrations with the generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, to explore design space scenarios, such as floorplan optimization and frequency versus voltage tradeoffs and the Cadence Joint Enterprise Data and AI (JedAI) Platform allows trend and insight analysis across different versions of the RTL or across previous project generations.

The key benefits are:

• Shortened TAT and increased productivity: 5X productivity improvement with faster physical estimates and reduced runtime compared to full production physical synthesis flow
• PPAC optimization: Up to 25% quality of results (QOR) improvement in RTL via early PPAC metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation
• User-Centric Solution: Provides designers with an efficient, user-friendly experience, offering physical design feedback, localization and categorization of violations, bottleneck analysis, and cross-probing between RTL, schematic, and layout
• Based on proven engines: Shares the same trusted engines as Cadence’s Innovus, Genus, and Joules solutions, enabling trusted prototype accuracy
• Powerful AI integrations: Integration with the generative-AI solution, Cadence Cerebrus Intelligent Chip Explorer, and the Cadence JedAI Platform

Early access engagements demonstrated Joules RTL Design Studio delivers great value and enables great potential for the future of RTL design.

Learn more about Cadence Joules RTL Design Studio.