Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

This morning we announced our next-generation Pegasus Verification System, the biggest breakthrough in SoC physical verification in more than 20 years. Pegasus is architected from the ground up to be a massively parallel, cloud-ready physical verification signoff solution. The groundbreaking technology delivers up to 10X improved design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours, helping designers deliver products to market faster.

Pegasus’s comes at the perfect timing when the industry faces two major challenges with the incumbent DRC tools. The growing complexity of the DRC rules and the exponential increase in the number of DRC operations has hit hard on the DRC tool performance. On the other side the single CPU speed has not improved for a long time and Cadence looked at both these angles and built Pegasus from scratch to deliver significant first in DRC technologies/use models.

Pegasus offers native cloud support and provides a massively parallel architecture, and combines a pipelined infrastructure with gigascale data flow and stream processing to deliver near-linear scalability over hundreds of CPUs. As many designs continue to grow in complexity, the Pegasus system is capable of scaling to meet the stringent performance and time-to-market goals of customers. With Pegasus, designers can run full-chip DRC on short notice without fear of impacting design schedules. 

 The key highlights of Pegasus are: 

• Massively parallel architecture provides unprecedented speed and capacity to easily run on hundreds of CPUs
• Delivers up to 10X improved performance across hundreds of CPUs for full-chip DRC signoff using foundry-certified rule decks to achieve 100 percent accurate results
• Demonstrated near-linear scalability on up to 960 CPUs, reducing DRC signoff turnaround time from days to hours
• Cloud-ready platform offers native cloud support that provides an elastic and flexible compute environment for customers facing aggressive time-to-market deadlines
• Seamlessly integrates with the Virtuoso custom design platform and Innovus Implementation System, which enables customers to run the Pegasus Verification System during multiple stages of the flow and full chip signoff

The new Pegasus Verification System continues to extend the organic innovation within the Cadence digital design and signoff suite. The suite includes a comprehensive full flow from synthesis through implementation and signoff, offering the fastest path to achieve power, performance, and area (PPA) targets across a wide variety of applications and vertical segments.

With Pegasus, DRC moves from a painful necessity to an easy final step. Pegasus ushers in a new DRC use model of running blocks over coffee and lunch breaks, and full chip faster than overnight.

I will be posting more blogs and sharing customer feedback in the coming days. I can’t wait to tell you more!

More details are on the Pegasus Verification System product page.